HD66781 Datasheet, PDF (125/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Serial Peripheral interface (SPI)
The Serial Peripheral Interface (SPI) is selected by setting IM3/2/1 pins to GND/Vcc1/GND levels
respectively. The SPI is available through the chip select line (CS), serial transfer clock line (SCL), serial
data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the
SPI mode, the DB17-2 pins, which are not used, must be fixed at either IOVcc level.
The HD66781 recognizes the start of data transfer at the falling edge of CS input to initiate the transfer of
start byte. It recognizes the end of data transfer at the rising edge of CS input. The HD66781 is selected
when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device
identification code assigned to the HD66781 are compared and both 6-bit data correspond. When selected,
the HD66781 starts taking in the subsequent data string. The setting for the least significant bit of the
identification code is made with the ID pin. The five upper bits of the identification code must be 01110.
Two different chip addresses must be assigned to the HD66781 because the seventh bit of the start byte is
assigned to a register select bit (RS). When RS = 0, index register write or status read is executed. When
RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte is to specify read
or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when the R/W bit is 1.
In the SPI mode, the data are written to GRAM after two-byte data transmission. The data are expanded
into 18 bits by adding one bit (the same data as the MSB of RB) to the LSB of RB data.
After receiving the start byte, the HD66781 starts to transmit or receive data by byte. The data transmission
adopts a format by which the MSB is first transmitted. All HD66781 instructions consist of 16 bits and
they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0). The data to
write to RAM are expanded into 18-bit data. After the start byte is received, the first byte is always fetched
as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the
instruction. The 4-byte data that are read from RAM right after the start byte are made invalid. The
HD66781 reads as valid data from the 5th-byte data.
Start Byte Format
Transmitted bits
S
1
2
3
4
5
6
7
8
Start byte format
Transmission Device ID code
start
RS R/W
0
1
1
1
0
ID
Note 1) ID bit is selected with the IM0/ID pin.
Table 64
RS R/W
0
0
0
1
1
0
1
1
Function
Set index register
Read status
Write instruction or RAM data
Read instruction or RAM data
Rev.0.5, July.31.2003, page 125 of 196