HD66781 Datasheet, PDF (22/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
The HD66781 incorporates DMA single address mode interface to keep control on the bus occupation ratio
when transferring a large volume of data. The DMA controller supporting a single address mode controls
the DACK pin of HD66781 to recognize out-enable signal (OE) for SRAM as a write strobe signal. The
HD66781 enables data transfer with less bus cycle by using a same bus cycle for a readout operation from
an external SRAM and a write operation to HD66781. See “DMA transfer single address mode” (p.131)
for details on controlling the execution of transfer and conditions in using this mode.
(2) External Display Interface (RGB I/F, VSYNC I/F)
The HD66781 incorporates RGB and VSYNC interfaces as an external interface for displaying moving
pictures. When the RGB-I/F is selected, the operation is synchronized with externally supplied signals,
VSYN C, HSYNC, and DOTCLK. The display data (PD17-0) are written in accordance with the data
enable signal (ENABLE). Accordingly, the display on the screen does not flicker when RAM data are
being updated internally.
When the VSYNC-I/F is selected, the operation is synchronized with internal clocks except frame
synchronization, which is synchronized with VSYNC signal. The display data is written to GRAM through
a system interface. In this case, there are constraints on the speed and methods of updating RAM data
when the VSYNC I/F is selected. For details, see the “External Display Interface” section (p.139).
The switch from and to the system interface is made through instructions. An optimum interface can be
selected for the kind of display (still and/or moving pictures). The display data are all written to GRAM
through the RGB-I/F. This enables transmission of data only when the display on the screen is being
updated, and thereby reduces the data transmission as well as consumption of power when a moving picture
is displayed.
(3) Address Counter (AC)
The address counter (AC) assigns the address to GRAM. When a set-address instruction is written to the
IR, the address information is sent from the IR to the AC. After writing data into GRAM, the AC is
automatically incremented or decremented by 1, while after data are read form GRAM, the AC is not
updated. Window address function enables data write only in the rectangular area of GRAM specified by
the window address.
(4) Graphic RAM (GRAM)
GRAM is a graphics RAM that stores 224,640-byte bit-pattern data, where one pixel is expressed by 18 bits.
Maximum 240 RGB x 320 can be displayed by using both main/sub panels. Besides data of 240 RGB x
320 lines for a base image, it can store OSD data of 240 RGB x 96 lines. The allocation of the numbers of
lines for a base image and an OSD image is changeable.
(5) Grayscale Voltage Generation Circuit
The grayscale voltage generation circuit generates an LCD drive voltage according to the grayscale level
set in the γ-correction register. Simultaneously 262,144 colors are available for display.
Rev.0.5, July.31.2003, page 22 of 196