HD66781 Datasheet, PDF (139/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
External Display Interface
The following interfaces are available as an external display interface (RGB interface). The interface is
selected by setting RIM1-0 bits. The RGB interface allows RAM access.
Table 65
RIM1 RIM0 RGB Interface
PD Pin
0
0
18-bit RGB interface
PD17-0
0
1
16-bit RGB interface
PD17-13, 11-1
1
0
6-bit RGB interface
PD17-12
1
1
Setting disabled
-
Note 1) It is not possible to use multiple interfaces at the same time.
Through the RGB-I/F, the display operation is in synchronization with VSYNC, HSYNC, and DOTCLK.
The RGB interface enables data transmission in high speed with low power consumption by only
overwriting the area that is needed to update in the high-speed write mode in combination with window
address function. Front and back porches must be set before and after the display period.
VSYNC ^ENABLE(V)
Back porch period (BP)
Moving picture
display area
Display period (NL)
HSYNC
DOTCLK
ENABLE(H)
PD17-0
Front porch period (FP)
Note 1) The front porch period continues until the next input
of VSYNC signal.
Note 2) The DOTCLK signal must be supplied consecutively.
VSYNC: Frame synchronization signal
HSYNC: Line synchronization signal
DOTCLK: DOT clock
ENABLE: Data enable signal
PD17-0: RGB(6:6:6)display data
Back porch period (BP):
Front porch period (FP):
Display Period
The numbers of raster-rows for 1 frame
14H≥BP≥2H
14H≥FP≥2H
FP + BP = 16H
NL≤320H
FP+NL+BP
Rev.0.5, July.31.2003, page 139 of 196