HD66781 Datasheet, PDF (131/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
DMA transfer Single Address mode
When connecting a microcomputer or an application processor, which are compliant to DMA transfer
single address mode, with the HD66781, and SRAM or pseudo SRAM, the HD66781 allows using same
bus cycle for data read from memory and data write to the HD66781. This reduces transfer time and
controls bus occupation ratio when transferring a large volume of data from external memory to a LCD
driver.
1. Pin functions in DMA single address mode
DACK: In DMA single address mode, it has the same function as CS in normal operation mode.
RD: Recognize write strobe (WR) internally when DACK is at the low level (active).
WR: Fix to High.
CS: Fix to High.
RS: Recognize a high level (data transfer) inside the HD66781 under any condition when DACK is at
the low level (active).
SH7300
CSn*
A21-0
WR
RD*
D15-0
DACK*
CSm*
CS*
1
RS
WR*
HD66781
RD*
DB15-0
DACK*
CS*
AD21-0
WE*
OE*
D15-0
SRAM
Interfacing with microcomputer and SRAM
Rev.0.5, July.31.2003, page 131 of 196