HD66781 Datasheet, PDF (133/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
3. Notes to the DMA single address mode
1. DACK*pin and CS*pin cannot be made at a low level (active) simultaneously.
2. Once starting a transfer in the DMA single address mode, no command access to the HD66781
will be allowed until the end of the transfer.
3. The DMA single adders mode must be used with the window address function to make sure the
number of data transfer in the DMA mode and the numbers of data in the specified window
address area correspond. .
4. After transferring in the DMA mode, wait at least for RAM write execution time (bus cycle
time in the normal write mode, t_cycw) before issuing a next instruction.
5. It is not possible to make a transfer form the HD66781 to external memory in the DMA single
address mode.
6. The DMA single address mode is compatible with the normal cycle still mode and the burst
mode.
Data transfer in DMA single address mode (cycle still mode)
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
R/W
CPU
DMAC
R/W
Data transfer in DMA single address mode (burst mode)
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
R/W
DMAC
R/W
DMAC
R/W
DMAC
R/W
CPU
DMAC
R/W
CPU
DMAC
R/W
DMAC
R/W
DMAC
R/W
CPU
Reference: Data transfer in DMA dual address mode (burst mode)
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
Read
DMAC
Write
DMAC
Read
DMAC
Write
DMAC
Read
DMAC
Write
CPU
Rev.0.5, July.31.2003, page 133 of 196