HD66781 Datasheet, PDF (12/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Signals
GND
AGND
RGND
IOVcc
Vcc
Vcc1
VREF
VDD
DDVDH
VDH
VGS
Vcom
TEST1
TEST2
TSC
OSC3
TS8-0
VTEST
VRTEST
VREFC1
VREFC2
Number of I/O
Pins
1
-
1
-
1
-
1
-
1
I
1
I
1
O
1
I/O
1
I
1
I
1
I
1
I
2
I
Connected Functions
to
Unused
pins
Power
supply
Power
supply
Power
supply
Power
supply
Power
supply
Power
supply
Ground for the logic side. GND = 0V
When assembled on COG, connect to GND on the FPC to avoid
-
effects from the noise.
Ground for the I/O side and analogue circuits other than logic
circuits and the internal GRAM, which operate with VDD voltage.
AGND = 0V
-
When assembled on COG, connect to GND on the FPC to avoid
effects from the noise.
Ground for the internal RAM. RGND = 0V. When assembled on
COG, connect to GND on the FPC to avoid effects from the
-
noise.
Supply with the power supply voltage for interface pins.
-
IOVcc = 1.7~3.3V. IOVcc ≤ Vcc1 ≤ Vcc
Power supply for internal logic regulator. Connect to an external
power supply of Vcc = 2.5~3.3V.
-
IOVcc ≤ Vcc1 ≤ Vcc
Power supply voltage for a deep standby control circuit and the
-
I/O side.
IOVcc ≤ Vcc1 ≤ Vcc
Power
supply
Reference voltage output for internal logic regulator. Leave
open.
Open
Stabilizing Power supply output for an internal logic. Do not connect to
Capacitor other than stabilizing capacitors.
-
HD66783 or Supply with a liquid crystal drive voltage through HD66783 or
HD667P21 HD667P21.
-
DDVDH = +4.0V~+5.9V
HD66783 or A reference level for a grayscale voltage generation circuit. Can
HD667P21 be supplied through HD66783 or HD667P21.
-
GND or
A reference level for a grayscale voltage generation circuit.
External
Connect to an external variable resistor to make a level
-
Resistor
adjustment for each panel.
HD66783 or Signal for equalization. Short-circuit all liquid crystal output
HD667P21 (S1~S720) to Vcom level (Hi-z) while EQ = High.
Leave open when Vcom < 0V.
GND
Test pins. Must be fixed to the GND level.
Open
-
1
I
GND
Test pin. Must be fixed to the GND level.
1
O Open
Test pin. Leave open.
9
O Open
Test pins. Leave open.
1
O Open
Test pin. Leave open.
1
O Open
Test pin. Leave open.
2
I
GND
Test pins. Must be fixed to GND level.
-
Open
Open
Open
Open
-
Rev.0.5, July.31.2003, page 12 of 196