HD66781 Datasheet, PDF (77/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Write Data to GRAM (R202h)
R/W RS
W1
The DB[17:0] pins are assigned to RAM write data (WD[17:0]) differently according to an interface.
RGB
interface
The DB[17:0] pins are assigned to RAM write data (WD[17:0]) differently according to an interface .
WD[17:0]: All data are expanded into 18 bits internally before being written to GRAM. The way of
expanding data into 18 bits is different according to the interface.
The grayscale level is selected according to the GRAM data. The address is automatically updated
according to the setting with the AM and I/D bits after data are written to GRAM. During the standby
mode, no access is allowed to GRAM. When the 8 or 16 bit interface modes are selected, the data in the
MSB of R and B pixels are also written to the LSB of R and B pixels respectively to expand the 8/16- bit
data into the 18-bit data internally.
During the RGB interface mode, when writing data to RAM through a system interface, make sure to avoid
conflicts between writing through the RGB interface and writing through system interface.
When the 18-bit RGB interface is selected, the18-bit data in PD17-0 bits are written, and 262,144 colors are
available. When the 16-bit RGB interface is selected, the data in the MSB of R and B pixels are also
written to the LSB of R and B pixels respectively, and 65,536 colors are available.
The upper 3 bits of OSD image data are used as a transmission-rate bit (α channel).
Table 46 BGR = 0
OSD ODF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 * R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
1 0 R5 R4 R3 R2 R1 α2 G5 G4 G3 G2 G1 α1 B5 B4 B3 B2 B1 α0
1 1 α2 α1 α0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Table 47 BGR =1
OSD ODF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 * B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R0
1 0 B5 B4 B3 B2 B1 α0 G5 G4 G3 G2 G1 α1 R5 R4 R3 R2 R1 α2
1 1 α0 α1 α2 B4 B3 B2 B1 B0 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0
Rev.0.5, July.31.2003, page 77 of 196