HD66781 Datasheet, PDF (180/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Power-saving drive settings
The HD66781 incorporates various settings for lower power consumption display. The low power
consumption and the quality of display are in trade-off, and the power-saving effect may vary depending on
the characteristics of a panel. Make an appropriate setting among the settings listed below taking the trade-
off into consideration.
1.
8-color display mode (COL)
When this mode is selected (COL [1:0] = 2’h2), voltage generation for grayscale levels other than V0 and
V63 levels is halted. In this mode, only 8 colors are available for display for saving power.
2.
Low power consumption display mode (COL, FRC)
Setting COL[1:0] to 2’h1 halts 32 amplifiers among V0 ~ V63 grayscale amplifiers to display with low
power consumption. In combination with the FRC mode setting, it is possible to realize display with low
power consumption in abundant colors.
In this mode, 250,047 colors are available with 18-bit, 16-bit x2, 9-bit x2, 8-bit x3 (RGB 6 bits each)
interfaces and 64,512 colors are available with 16-bit x1, 8-bit x2 interfaces and SPI (R, B: 5 bits, G: 6 bits).
Using this mode with short screen refreshing cycle may affect the quality of display. Consider the trade-off
between the display quality and power-saving effects before use. See the “Low power consumption display
mode” (p.169) for details.
3.
Partial display (OSD)
The partial display is made with OSD and base image display off setting (BASEE = 0). Display operation
is limited to the partial display area to save power. Power saving effects will increase as the number of
partial display lines decreases. Also, see “Partial Display Function”(p.139) for details.
4.
Non-lit drive setting
The non-lit drive setting is available for partial display and allows specifying the kind of source outputs in
the non-lit drive area with PTS bits. Also, in the non-lit drive area, grayscale generation amplifier is halted
and step-up clock cycle is slowed down to half.
PTG bits can specify the scan mode of gate bus lines in the non-lit drive area. In the interval gate scan
mode, gate bus lines are scanned by the frame cycle specified by ISC bits to hold power consumption
required for scanning gate bus lines to minimum. The longer scan cycle may affect the quality of display.
Make an appropriate setting by taking trade-off between power-saving effects and display quality.
Rev.0.5, July.31.2003, page 180 of 196