HD66781 Datasheet, PDF (138/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
From Internal clock operation
to VSYNC interface mode
From VSYNC interface mode
to Internal clock operation
Internal clock operation
HWM = 1, AM = 0
Address Setting
VSYNC interface mode setting
(DM1-0=10, RM=0)
Index resister setting (R202)h
Wait more than 1 frame
VSYNC interface
Writing RAM data
VSYNC interface operation
Display operation
in synchronization with
the internal clocks
The settings in DM1-0, RM
become valid after displaying
one frame.
VSYNC interface operation
Internal clock mode setting
(DM1-0 = 00, RM=0)
Wait more than 1 frame
Internal clock operation
Display operation
in synchronization with
VSYNC
The settings in DM1-0, RM
become valid after displaying
one frame.
Display operation
in synchronization with
the internal clocks
Note: VSYNC signal must be supplied for at least one frame
when switching to the internal clock operation.
Display operation
in synchronization with
VSYNC
Internal clock mode setting
(DM1-0 = 00, RM=0)
Wait more than 1 frame
Internal clock operation
Note: VSYNC signal must be supplied before setting DM1-0, RM
when switching to the VSYNC I/F mode.
Transition between VSYNC and Internal clock operation modes
Rev.0.5, July.31.2003, page 138 of 196