HD66781 Datasheet, PDF (94/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
OSD control instructions
OSD image 1 display position (R500h)
OSD image 1 RAM Address /Start line Address (R501h)
OSD image 1 RAM Address /End line Address (R502h)
OSD image 2 display position (R503h)
OSD image 2 RAM Address/Start line Address (R504h)
OSD image 2 RAM Address/End line Address (R505h)
OSD image 3 display position (R506h)
OSD image 3 RAM Address/Start line Address (R507h)
OSD image 3 RAM Address/End line Address (R508h)
R / W RS
R500 W 1
R501 W 1
R502 W 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
0
0
0
0
0
0
0
ODP ODP ODP ODP ODP ODP ODP ODP ODP
0 [8] 0 [7] 0 [6] 0 [5] 0 [4] 0 [3] 0 [2] 0 [1] 0 [0]
0
0
0
0
0
0
0
OSA OSA OSA OSA OSA OSA OSA OSA OSA
0 [8] 0 [7] 0 [6] 0 [5] 0 [4] 0 [3] 0 [2] 0 [1] 0 [0]
0
0
0
0
0
0
0
OEA OEA OEA OEA OEA OEA OEA OEA OEA
0 [8] 0 [7] 0 [6] 0 [5] 0 [4] 0 [3] 0 [2] 0 [1] 0 [0]
R503 W 1
R504 W 1
R505 W 1
0
0
0
0
0
0
0
ODP ODP ODP ODP ODP ODP ODP ODP ODP
1 [8] 1 [7] 1 [6] 1 [5] 1 [4] 1 [3] 1 [2] 1 [1] 1 [0]
0
0
0
0
0
0
0
OSA OSA OSA OSA OSA OSA OSA OSA OSA
1 [8] 1 [7] 1 [6] 1 [5] 1 [4] 1 [3] 1 [2] 1 [1] 1 [0]
0
0
0
0
0
0
0
OEA OEA OEA OEA OEA OEA OEA OEA OEA
1 [8] 1 [7] 1 [6] 1 [5] 1 [4] 1 [3] 1 [2] 1 [1] 1 [0]
R506 W 1
R507 W 1
R508 W 1
0
0
0
0
0
0
0
ODP ODP ODP ODP ODP ODP ODP ODP ODP
2 [8] 2 [7] 2 [6] 2 [5] 2 [4] 2 [3] 2 [2] 2 [1] 2 [0]
0
0
0
0
0
0
0
OSA OSA OSA OSA OSA OSA OSA OSA OSA
2 [8] 2 [7] 2 [6] 2 [5] 2 [4] 2 [3] 2 [2] 2 [1] 2 [0]
0
0
0
0
0
0
0
OEA OEA OEA OEA OEA OEA OEA OEA OEA
2 [8] 2 [7] 2 [6] 2 [5] 2 [4] 2 [3] 2 [2] 2 [1] 2 [0]
ODP0[8:0]: ODP0 : Set the display position of OSD image 1.
ODP1[8:0]: ODP1 : Set the display position of OSD image 2.
ODP2[8:0]: ODP2 : Set the display position of OSD image 3.
The display areas for OSD images 1, 2, 3 should not overlap one another. Set each area as follows.
Display area of OSD image 1: ODP0, ODP0+(OEA0 – OSA0)
Display area of OSD image 2: ODP1, ODP1+(OEA1 – OSA1)
Display area of OSD image 3: ODP2, ODP2+(OEA2 – OSA2)
Make sure that
display area of OSD image 1 < Display area of OSD image 2 < Display area of OSD image 3.
If ODP0 is set “9’h000”, OSD image 1 is displayed from the start line of the base image on the first panel.
The OSD is not available during interlaced drive (FLD = 2’h3).
OSA0[8:0] OEA0[8:0]: OSA0, OEA0 : Set the start line address and end line address for display RAM
area of the OSD image 1.
Rev.0.5, July.31.2003, page 94 of 196