HD66781 Datasheet, PDF (100/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Preliminary
Gate pins
Panel position
n+1
Base image
RAM address
OSD image
RAM address
SCN
ODP0
BSA
OSA0
RAM write
Address
(HSA,HEA)
LCD
n+m
GS
ODP1
Base
image
OEA0
OSA1
NL+SCN
ODP2
BEA
OEA1
OSA2
OEA2
RAM Address, display position and drive position
Window
Address
(VSA,VEA)
Notes to the setting of panel control registers
The HD66781 has some constrains in setting the coordinate with regard to the display data, position, and
OSD.
Screen settings
The following equation must be observed in making a setting for the screen.
NL ≤ 320 lines
0 ≤ SCN < SCN+NL ≤ 320 lines
Base image display
Base image is displayed from the first line of each panel. Base image display start position: SCN = BSA
Set the base image RAM area (BSA, BEA) equal to or more than the number of lines (NL) required driving
a panel. NL ≤ BEA – BSA
OSD image display
Set the OSD image RAM area (OSAx, OEAx) not to overlap one another. Set the OSD positions not to
overlap one another.
0 ≤ ODP0 ≤ ODP0+ n x (OEA0 – OSA0+1) - 1<
ODP1 ≤ ODP1+ n x (OEA1 – OSA1+1) - 1<
ODP2 ≤ ODP2+ n x (OEA2 – OSA2+1) - 1≤ NL
n: OSD image magnification scale
The OSD images are displayed 100% when base image is turned off (BASEE = 0). The arrangement of α
channels is also changed when changing RGB order to BGR. The OSD data are read out in the format
when ODF is set to 0. During interlaced drive (FLD = 2’h3), OSD and α blending functions are not
available.
Rev.0.5, July.31.2003, page 100 of 196