HD66781 Datasheet, PDF (59/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Gate Driver/LTPS LCD Panel Interface Control 4 (R013h)
Preliminary
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
DPW DPW DPW DPW DPW
DPTI DPTI
0
0 0 _{I4 I3 I2 I1 I0}
0
0
00
00
1
0
DPTI[1:0]: Specify the rising position of DISPTMG during display operation with internal clocks (DM =
2’h0 or 2’h2).
DPWI[4:0]: DPWI bits specifies the width of “High” of DISPTMG during display operation with internal
clocks (DM = 2’h0 or 2’h2) when LTPS = 1. The setting of this register is invalid when LTPS = 0. In this
case, the falling position of CL1 is at a reference point.
See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD
panel interface are controlled by these settings.
Table 37
DPTI[1:0] DISPTMG Rising position
DPWI[4:0] DISPTMG “High” width
2’h0
0 clock
5’h00
0 clock
2’h1
1 clock
5’h01
1 clock
2’h2
2 clocks
5’h02
2 clocks
2’h3
3 clocks
5’h03
3 clocks
:
:
5’h1D
29 clocks
5’h1E
30 clocks
5’h1F
31 clocks
Note 1) The clocks in the tables are measured from a reference point. The reference point is the position
where SFTCLK rises when the rising position of SFTCLK is set to 0 clock.
Note 2) The gate non-overlap period can be set to 0 when DPTI = “2’h0” and DPWI is set to the number of
clocks more than that of the 1H period.
Rev.0.5, July.31.2003, page 59 of 196