HD66781 Datasheet, PDF (62/196 Pages) Renesas Technology Corp – 720-channel Source Driver for a-Si TFT/Low Temperature Poly-Si TFT Panels with 262,144-color display RAM

HD66781
Gate Driver/LTPS LCD Panel Interface Control 7 (R017h)
Preliminary
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
0
SWE SWE SWE SWE SWE SWE
0 _{54 3}
21 0 ⁰
0
00
0 STE2 STE1 STE0
STE[2:0]: STE bits specifies the rising position of SFTCLK1/2 during display operation with DOTCLK
(DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the rising
position of CL1 is 8 clocks away from a reference point.
SWE[5:0]: SWE bits specifies the width of “High” of SFTCLK1/2 during display operation with
DOTCLK (DM = 2’h1) when LTPS = 1. The register setting is invalid when LTPS = 0. In this case, the
falling position of CL1 is at a reference point.
See the figures (page 66, 67) with regard to how the signal waveform of each gate driver and LTPS LCD
panel interface are controlled by these settings.
Table 40
STE[2:0] CL1/SFTCLK1,2 Rising position SWE[5:0] CL1/SFTCLK1,2 “High” width
3’h0
0 clock
6’h00
0 clock
3’h1
1 clock
6’h01
1 clock
3’h2
2 clocks
6’h02
2 clocks
3’h3
3 clocks
6’h03
3 clocks
3’h4
4 clocks
:
:
3’h5
5 clocks
6’h3D
61 clocks
3’h6
6 clocks
6’h3E
62 clocks
3’h7
7 clocks
6’h3F
63 clocks
Note 1) The clocks in the tables are DOTCLK / division ratio for the 1H period, measured from a reference
point. The reference point is the position where SFTCLK rises when the rising position of SFTCLK is
set to 0 clock.
Rev.0.5, July.31.2003, page 62 of 196