R0E417250MCU00 Datasheet, PDF (123/228 Pages) Renesas Technology Corp – E100 Emulator MCU Unit for H8SX/1700 Series

R0E417250MCU00 User’s Manual
5. Debugging Functions
The following items are shown in the Trace window (in bus display mode).
Table 5.13 Items shown in the Trace window
Column
Description
Cycle
Number of the cycle within trace memory. By default, the number of the last cycle to have been acquired
is 0, and earlier cycles are assigned progressively lower numbers in sequence, i.e. –1, –2, etc. If a delay
count is set, the cycle on which the trace stop condition is met is numbered 0 and the cycles that were
executed until the program actually stopped (cycles during a delay period) are assigned progressively
larger numbers +1, +2, etc. in sequence up to the last cycle to be acquired.
Label
Label corresponding to the address (displayed only when a label has been set)
Address
Address on the address bus
Data
Data on the data bus (in hexadecimal)
Size
Unit of access (byte, word, or longword)
R/W
Data bus state, indicated as “R” for reading, “W” for writing, or “–” for no access
RWT
Whether the bus cycle is valid or not. The value “0” indicates a valid bus cycle. The Address and Data
information is valid when RWT is “0”.
Status
Current mode of the target MCU.
NORMAL
Normal operation
S-ACT
Subactive mode
SLEEP
Sleep mode
S_SLEEP
Subsleep mode
AMCS
All-module clock-stop mode
S-STBY
Software standby mode
H-STBY
Hardware standby mode
D-STBY
Deep standby mode
-
Other
*
Impossible combination with ACTIVE
Active
Action taken by the target MCU.
DMAC
Access by DMAC operation
DTC
Access by DTC operation
HUDI
Access by HUDI operation
DATA
Data access by CPU operation
FETCH
Instruction fetch by CPU operation
STACK
Stack access by CPU operation
-
Other
*
Impossible combination with STATUS
REJ10J1831-0200 Rev.2.00 Jun.1, 2009
Page 123 of 228