CP3BT10 Datasheet, PDF(67/210 Page) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

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CP3BT10 Datasheet, PDF (67/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

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14.1.6 Port High Drive Strength Register (PxHDRV)

The PxHDRV register is a byte-wide, read/write register that

controls the slew rate of the corresponding pins. The high

drive strength function is enabled when the corresponding

bits of the PxHDRV register are set. In both GPIO and alter-

nate function modes, the drive strength function is enabled

by the PxHDRV registers. At reset, the PxHDRV registers

are cleared, making the ports low speed.

PxHDRV

The PxHDRV bits control whether output pins

are driven with slow or fast slew rate.

0 â Slow slew rate.

1 â Fast slew rate.

14.1.7 Port Alternate Function Select Register

(PxALTS)

The PxALTS register selects which of two alternate func-

tions are selected for the port pin. These bits are ignored

unless the corresponding PxALT bits are set. Each port pin

can be controlled independently.

PxALTS

The PxALTS bits select among two alternate

functions. Table 31 shows the mapping of the

PxALTS bits to the alternate functions. Un-

used PxALTS bits must be clear.

Table 31 Alternate Function Select

Port Pin

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

PH6

PH7

PI0

PI1

PI2

PI3

PI4

PI5

PI6

PI7

PxALTS = 0 PxALTS = 1

RXD

TXD

RTS

CTS

Reserved

SRFS

Reserved

MSK

MDIDO

MDODI

MWCS

SCK

SFS

STD

SRD

RFSYNC

RFCE

BTSEQ1

SCLK

SDAT

SLE

WUI9

WUI10

WUI11

WUI12

WUI13

NMI

WUI14

WUI15

TIO1

TIO2

TIO3

TIO4

TIO5

TIO6

TIO7

TIO8

Reserved

SRCLK

Reserved

BTSEQ2

BTSEQ3

14.2 OPEN-DRAIN OPERATION

A port pin can be configured to operate as an inverting

open-drain output buffer. To do this, the CPU must clear the

bit in the data output register (PxDOUT) and then use the

port direction register (PxDIR) to set the value of the port

pin. With the direction register bit set (direction = out), the

value zero is forced on the pin. With the direction register bit

clear (direction = in), the pin is placed in the TRI-STATE

mode. If desired, the internal weak pull-up can be enabled

to pull the signal high when the output buffer is in TRI-

STATE mode.

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