CP3BT10 Datasheet, PDF (55/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

11.7.3 Fault-Tolerant External Reset
11.8 CLOCK AND RESET REGISTERS
An external reset circuit based on the LM3710 Microproces-
sor Supervisory Circuit is shown in Figure 8. It provides a
high level of fault tolerance in that it provides the ability to
monitor both the VCC supply for the core logic and the IO-
VCC supply. It also provides a low-voltage indication for the
IOVCC supply and an external watchdog timer.
Core VCC
(2.5V)
278k Ω
Power Fail
Input (PFI)
332k Ω
IOVCC
Reset Output
LM3710
Supervisory
Power Fail Output (PFO)
Circuit with
Power-Fail
Low Line Output (LLO)
and Low-Line
Detection
Watchdog Input (WDI)
IOVCC
VCC
CP3BT1x
RESET
NMI
IRQ
GPIO
Table 25 lists the clock and reset registers.
Table 25 Clock and Reset Registers
Name
CRCTRL
PRSFC
PRSSC
PRSAC
Address
FF FC40h
FF FC42h
FF FC44h
FF FC46h
Description
Clock and Reset
Control Register
High Frequency Clock
Prescaler Register
Low Frequency Clock
Prescaler Register
Auxiliary Clock
Prescaler Register
11.8.1 Clock and Reset Control Register (CRCTRL)
Manual
Reset
The CRCTRL register is a byte-wide read/write register that
GND
controls the clock selection and contains the power-on reset
status bit. At reset, the CRCTRL register is initialized as de-
DS510 _{scribed below:}
Figure 8. Fault-Tolerant External Reset
76
5
4
3
2
1
0
The signals shown in Figure 8 are:
Reserved POR ACE2 ACE1 PLLPWD FCLK SCLK
„ Core VCC—the 2.5V power supply rail for the core logic.
„ IOVCC—the 2.5–3.3V power supply rail for the I/O logic.
„ Watchdog Input (WDI)—this signal is asserted by the
CP3BT10 at regular intervals to indicate normal opera-
tion. A general-purpose I/O (GPIO) port may be used to
provide this signal. If the internal watchdog timer in the
CP3BT10 is used, then the LM3704 Microprocessor Su-
pervisory Circuit can provide the same features as the
LM3710 but without the watchdog timer.
„ RESET—an active-low reset signal to the CP3BT10.
The LM3710 is available in versions with active pullup or
an open-drain RESET output.
„ Power-Fail Input (PFI)—this is a voltage level derived
from the Core VCC power supply rail through a simple
resistor divider network.
„ Power-Fail Output (PFO)—this signal is asserted when
the voltage on PFI falls below 1.225V. PFO is connected
to the non-maskable interrupt (NMI) input on the
CP3BT10. A system shutdown routine can then be in-
voked by the NMI handler.
„ Low Line Output (LLO)—this signal is asserted when the
main IOVCC level fails below a warning threshold voltage
but remains above a reset detection threshold. This sig-
nal may be routed to the NMI input on the CP3BT10 or
to a separate interrupt input.
SCLK
FCLK
PLLPWD
These additional status and feedback mechanisms allow
the CP3BT10 to recover from software hangs or perform
system shutdown functions before being placed into reset.
The standard reset threshold for the LM3710 is 3.08V with
other options for different watchdog timeout and reset time-
outs. The selection of these values are much more applica-
tion-specific. The combination of a watchdog timeout period
of 1600 ms and a reset period of 200 ms is a reasonable
starting point.
The Slow Clock Select bit controls the clock
source used for the Slow Clock.
0 – Slow Clock driven by prescaled Main
Clock.
1 – Slow Clock driven by 32.768 kHz oscilla-
tor.
The Fast Clock Select bit selects between the
12 MHz Main Clock and the PLL as the source
used for the System Clock. After reset, the
Main Clock is selected. Attempting to switch to
the PLL while the PLLPWD bit is set (PLL is
turned off) is ignored. Attempting to switch to
the PLL also has no effect if the PLL output
clock has not stabilized.
0 – The System Clock prescaler is driven by
the output of the PLL.
1 – The System Clock prescaler is driven by
the 12-MHz Main Clock. This is the de-
fault after reset.
The PLL Power-Down bit controls whether the
PLL is active or powered down (Stop PLL sig-
nal asserted). When this bit is set, the on-chip
PLL stays powered-down. Otherwise it is pow-
ered-up or it can be controlled by the Power
Management Module, respectively. Before
software can power-down the PLL in Active
mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD
bit while the FCLK bit is clear is ignored. The
FCLK bit cannot be cleared until the PLL clock
has stabilized. After reset this bit is set.
0 – PLL is active.
1 – PLL is powered down.
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