CP3BT10 Datasheet, PDF (30/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

7.0 System Configuration Registers
The system configuration registers control and provide sta-
tus for certain aspects of device setup and operation, such
as indicating the states sampled from the ENV[2:0] inputs.
The system configuration registers are listed in Table 11.
Table 11 System Configuration Registers
Name
MCFG
MSTAT
Address
FF F910h
FF F914h
Description
Module Configuration
Register
Module Status
Register
7.1 MODULE CONFIGURATION REGISTER
(MCFG)
The MCFG register is a byte-wide, read/write register that
selects the clock output features of the device.
The register must be written in active mode only, not in pow-
er save, HALT, or IDLE mode. However, the register con-
tents are preserved during all power modes.
The MCFG register format is shown below.
MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew
rate of the output drivers for the ENV[2:0],
RDY, RFDATA, and TDO pins. To minimize
noise, the slow slew rate is recommended.
0 – Fast slew rate.
1 – Slow slew rate.
MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew
rate of the output drivers for the A[21:0], RD,
SEL[2:1], and WR[1:0] pins. Memory speeds
for the CP3BT10 are characterized with fast
slew rate. Slow slew rate reduces the avail-
able memory access time by 5 ns.
0 – Fast slew rate.
1 – Slow slew rate.
7.2 MODULE STATUS REGISTER (MSTAT)
The MSTAT register is a byte-wide, read-only register that
indicates the general status of the device. The MSTAT reg-
ister format is shown below.
7
5
4
3
2
1
0
Reserved DPGMBUSY PGMBUSY OENV2 OENV1 OENV0
76
5
4
32
10
Res.
MEM_IO
_SPEED
MISC_IO
_SPEED
USB
_ENABLE
SCLK
OE
MCLK
OE
PLLCLK
OE
EXI
OE
EXIOE
The EXIOE bit controls whether the external
bus is enabled in the IRE environment for im-
plementing the I/O Zone (FF FB00h–FF
FBFFh).
0 – External bus disabled.
1 – External bus enabled.
PLLCLKOE The PLLCLKOE bit controls whether the PLL
clock is driven on the ENV0/PLLCLK pin.
0 – ENV0/PLLCLK pin is high impedance.
1 – PLL clock driven on ENV0/PLLCLK.
MCLKOE The MCLKOE bit controls whether the Main
Clock is driven on the ENV1/CPUCLK pin.
0 – ENV1/CPUCLK pin is high impedance.
1 – Main Clock is driven on ENV1/CPUCLK.
SCLKOE The SCLKOE bit controls whether the Slow
Clock is driven on the ENV2/SLOWCLK pin.
0 – ENV2/SLOWCLK pin is high impedance.
1 – Slow Clock driven on ENV2/SLOWCLK.
USB_ENABLE The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the Function Word (see Section 8.4.1), and
the USB_ENABLE bit in the MCFG register.
0 – External USB transceiver forced into low-
power mode.
1 – Transceiver power mode dependent on
USB controller status and programming
of the Function Word. (This is the state of
the USB_ENABLE bit after reset.)
OENV[2:0]
PGMBUSY
DPGMBUSY
The Operating Environment bits hold the
states sampled from the ENV[2:0] input pins
at reset. These states are controlled by exter-
nal hardware at reset and are held constant in
the register until the next reset.
The Flash Programming Busy bit is automati-
cally set when either the program memory or
the data memory is being programmed or
erased. It is clear when neither of the memo-
ries is busy. When this bit is set, software must
not attempt to program or erase either of
these two memories. This bit is a copy of the
FMBUSY bit in the FMSTAT register.
0 – Flash memory is not busy.
1 – Flash memory is busy.
The Data Flash Programming Busy indicates
that the flash data memory is being erased or
a pipelined programming sequence is current-
ly ongoing. Software must not attempt to per-
form any write access to the flash program
memory at this time, without also polling the
FSMSTAT.FMFULL bit in the flash memory in-
terface. The DPGMBUSY bit is a copy of the
FMBUSY bit in the FSMSTAT register.
0 – Flash data memory is not busy.
1 – Flash data memory is busy.
www.national.com
30