CP3BT10 Datasheet, PDF (121/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

UEEI
The Enable Receive Error Interrupt bit, when
set, enables generation of an interrupt when
the hardware sets the UERR bit in the USTAT
register.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
19.3.11 UART Sample Position Register (USPOS)
The USPOS register is a byte-wide, read/write register that
specifies the sample position when the USMD bit in the
UMDSL2 register is set. At reset, the USPOS register is ini-
tialized to 06h. The register format is shown below.
19.3.9 UART Oversample Rate Register (UOVR)
The UOVR register is a byte-wide, read/write register that
specifies the oversample rate. At reset, the UOVR register
is cleared. The register format is shown below.
7
4
3
0
Reserved
UOVSR
UOVSR
The Oversampling Rate field specifies the
oversampling rate, as given in the following ta-
ble.
UOVSR3:0
Oversampling Rate
7
4
3
0
Reserved
USAMP
USAMP
The Sample Position field specifies the over-
sample clock period at which to take the first
of three samples for sensing the value of data
bits. The clocks are numbered starting at 0
and may range up to 15 for 16× oversampling.
The maximum value for this field is (oversam-
pling rate - 3). The table below shows the
clock period at which each of the three sam-
ples is taken, when automatic sampling is en-
abled (UMDSL2.USMD = 0).
0000–0110
16
0111
7
Oversampling Rate
Sample Position
123
1000
8
7
234
1001
9
8
234
1010
10
9
345
1011
11
10
345
1100
12
11
456
1101
13
12
456
1110
14
13
567
1111
15
14
567
19.3.10 UART Mode Select Register 2 (UMDSL2)
The UMDSL2 register is a byte-wide, read/write register that
controls the sample mode used to recover asynchronous
data. At reset, the UOVR register is cleared. The register
format is shown below.
7
1
0
Reserved
USMD
15
678
16
678
The USAMP field may be used to override the
automatic selection, to choose any other clock
period at which to start taking the three sam-
ples.
USMD
The USMD bit controls the sample mode for
asynchronous transmission.
0 – UART determines the sample position au-
tomatically.
1 – The USPOS register determines the sam-
ple position.
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