CP3BT10 Datasheet, PDF (53/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

The Stop Main Osc signal from the Power Management
Module stops and starts the high-frequency oscillator.
When this signal is asserted, it presets the 14-bit timer to
3FFFh and stops the high-frequency oscillator. When the
signal goes inactive, the high-frequency oscillator starts and
the 14-bit timer counts down from its preset value. When the
timer reaches zero, it stops counting and asserts the Good
Main Clock signal.
11.3 SLOW CLOCK
The Slow Clock is necessary for operating the device in re-
duced power modes and to provide a clock source for mod-
ules such as the Timing and Watchdog Module.
The Slow Clock operates in a manner similar to the Main
Clock. The Stop Slow Osc signal from the Power Manage-
ment Module stops and starts the low-frequency (32.768
kHz) oscillator. When this signal is asserted, it presets a 6-
bit timer to 3Fh and disables the low-frequency oscillator.
When the signal goes inactive, the low-frequency oscillator
starts, and the 6-bit timer counts down from its preset value.
When the timer reaches zero, it stops counting and asserts
the Good Slow Clock signal, which indicates that the Slow
Clock is stable.
For systems that do not require a reduced power consump-
tion mode, the external crystal network may be omitted for
the Slow Clock. In that case, the Slow Clock can be synthe-
sized by dividing the Main Clock by a prescaler factor. The
prescaler circuit consists of a fixed divide-by-2 counter and
a programmable 8-bit prescaler register. This allows a
choice of clock divisors ranging from 2 to 512. The resulting
Slow Clock frequency must not exceed 100 kHz.
The PRSFC register must not be modified while the System
Clock is derived from the PLL Clock. The System Clock
must be derived from the low-frequency oscillator clock
while the MODE field is modified.
11.5 SYSTEM CLOCK
The System Clock drives most of the on-chip modules, in-
cluding the CPU. Typically, it is driven by the Main Clock, but
it can also be driven by the PLL. In either case, the clock sig-
nal is passed through a programmable divider (scale factors
from ÷1 to ÷16).
11.6 AUXILIARY CLOCKS
Auxiliary Clock 1 and Auxiliary Clock 2 are generated from
Main Clock for use by certain peripherals. Auxiliary Clock 1
is available for the Bluetooth controller and the Advanced
Audio Interface. Auxiliary Clock 2 is available for the CVSD/
PCM transcoder. The Auxiliary clocks may be configured to
keep these peripherals running when the System Clock is
slowed down or suspended during low-power modes.
11.7 POWER-ON RESET
The CP3BT10 has specific Power On Reset (POR) timing
requirements that must be met to prevent corruption of the
on-chip flash program and data memories. This timing se-
quence shown in Figure 5.
All reset circuits must ensure that this timing sequence is al-
ways maintained during power-up and power-down. The
design of the power supply also affects how this sequence
is implemented.
The power-up sequence is:
A software-programmable multiplexer selects either the
prescaled Main Clock or the 32.768 kHz oscillator as the
Slow Clock. At reset, the prescaled Main Clock is selected,
ensuring that the Slow Clock is always present initially. Se-
lection of the 32.768 kHz oscillator as the Slow Clock dis-
ables the clock prescaler, which allows the CLK1 oscillator
to be turned off, which reduces power consumption and ra-
diated emissions. This can be done only if the module de-
tects a toggling low-speed oscillator. If the low-speed
oscillator is not operating, the prescaler remains available
as the Slow Clock source.
11.4 PLL CLOCK
The PLL Clock is generated by the PLL from the 12 MHz
Main Clock by applying a multiplication factor of ×3, ×4, or
×5. The USB interface is clocked directly by the PLL Clock
and requires a 48 MHz clock, so a ×4 scaling factor must be
used if the USB interface is active.
To enable the PLL:
1. Set the PLL multiplication factor in PRFSC.MODE.
2. Clear the PLL power-down bit CRCTRL.PLLPWD.
3. Clear the high-frequency clock select bit CRC-
TRL.FCLK.
4. Read CRCTRL.FCLK, and go back to step 3 if not clear.
The CRCTRL.FCLK bit will be clear only after the PLL has
stabilized, so software must repeat step 3 until the bit is
clear. The clock source can be switched back to the Main
Clock by setting the CRCTRL.FCLK bit.
1. The RESET pin must be held low until both IOVCC and
VCC have reached the minimum levels specified in the
DC Characteristics section. IOVCC and VCC are al-
lowed to reach their nominal levels at the same time
which is the best-case scenario.
2. After both of these supply voltage rails have met this
condition, then the RESET pin may be driven high. At
power-up an internal 14-bit counter is set to 3FFFh and
begins counting down to 0 after the crystal oscillator
becomes stable. When this counter reaches 0, the on-
chip RESET signal is driven high unless the external
RESET pin is still being held low. This prevents the
CP3BT10 from coming out of reset with an unstable
clock source.
The power-down sequence is:
1. The RESET pin must be driven low as soon as either
the IOVCC or VCC voltage rail reaches the minimum
levels specified in the DC Characteristics.
2. The RESET pin must then be held low until the Main
Clock is stopped. The Main Clock will decay with the
same profile as IOVCC.
Meeting the power-down reset conditions ensures that soft-
ware will not be executed at voltage levels that may cause
incorrect program execution or corruption of the flash mem-
ories. This situation must be avoided because the Main
Clock decays with the IOVCC supply rather than stopping
immediately when IOVCC falls below the minimum specified
level.
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