CP3BT10 Datasheet, PDF (51/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

11.0 Triple Clock and Reset
The Triple Clock and Reset module generates a 12 MHz
Main Clock and a 32.768 kHz Slow Clock from external
crystal networks or external clock sources. It provides vari-
ous clock signals for the rest of the chip. It also provides the
main system reset signal, a power-on reset function, Main
Clock prescalers to generate two additional low-speed
clocks, and a 32-kHz oscillator start-up delay.
Figure 3 is block diagram of the Triple Clock and Reset mod-
ule.
Reset
TWM (Invalid Watchdog Service)
Flash Interface (Program/Erase Busy)
External Reset
Power-On-Reset
Module (POR)
Stop Main Osc.
X1CKI
X1CKO
High Frequency
Oscillator
Preset
Start-Up-Delay
14-Bit Timer
4-Bit Aux1
Prescaler
4-Bit Aux2
Prescaler
Main Clock
X2CKI
Low Frequency
Oscillator
X2CKO
Div.
8-Bit
by 2
Prescaler
Slow Clock Prescaler
Start-Up-Delay
8-Bit Timer
Preset
Reset
Module
Device Reset
Stretched
Reset
Stop Main Osc
Good Main Clock
Auxiliary Clock 1
Auxiliary Clock 2
Time-out
Slow Clock
Slow Clock
Select
Good Slow Clock
Fast Clock
Prescaler
4-Bit
Prescaler
Stop Slow Osc
Bypass
32 kHz Osc
System Clock
Fast Clock
Select
PLL
(x3, x4, or x5)
Stop PLL
PLL Clock
Bypass PLL
Good PLL Clock
Stop PLL
Figure 3. Triple Clock and Reset Module
DS006
51
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