CP3BT10 Datasheet, PDF (35/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

rial debug interface. If a majority of the WR-
PROT bits are set, write access is allowed.
8.5 FLASH MEMORY INTERFACE
REGISTERS
Table 18 Flash Memory Interface Registers
Program
Memory
Data
Memory
Description
There is a separate interface for the program flash and data
flash memories. The same set of registers exist in both in-
terfaces. In most cases they are independent of each other,
but in some cases the program flash interface controls the
interface for both memories, as indicated in the following
sections. Table 18 lists the registers.
Table 18 Flash Memory Interface Registers
Program
Memory
FMIBAR
FF F940h
FMIBDR
FF F942h
FM0WER
FF F944h
Data
Memory
FSMIBAR
FF F740h
FSMIBDR
FF F742h
FSM0WER
FF F744h
Description
Flash Memory
Information Block
Address Register
Flash Memory
Information Block
Address Register
Flash Memory 0
Write Enable Register
FMRCV
FF F962h
FMAR0
FF F964h
FMAR1
FF F966h
FMAR2
FF F968h
FSMRCV
FF F762h
FSMAR0
FF F764h
FSMAR1
FF F766h
FSMAR2
FF F768h
Flash Memory
Recovery Time
Reload Register
Flash Memory
Auto-Read Register 0
Flash Memory
Auto-Read Register 1
Flash Memory
Auto-Read Register 2
8.5.1 Flash Memory Information Block Address
Register (FMIBAR/FSMIBAR)
The FMIBAR register specifies the 8-bit address for read or
write access to an information block. Because only word ac-
cess to the information blocks is supported, the least signif-
icant bit (LSB) of the FMIBAR must be 0 (word-aligned). The
hardware automatically clears the LSB, without regard to
the value written to the bit. The FMIBAR register is cleared
after device reset. The CPU bus master has read/write ac-
cess to this register.
FM1WER
FF F946h
N/A
Flash Memory 1
Write Enable Register ₁₅
8
7
0
FMCTRL
FSMCTRL
Flash Memory
Reserved
IBA
FF F94Ch
FF F74Ch
Control Register
FMSTAT
FF F94Eh
FMPSR
FF F950h
FMSTART
FF F952h
FSMSTAT
FF F74Eh
FSMPSR
FF F750h
FSMSTART
FF F752h
Flash Memory
IBA
Status Register
Flash Memory
Prescaler Register
Flash Memory Start
Time Reload Register
The Information Block Address field holds the
word-aligned address of an information block
location accessed during a read or write
transaction. The LSB of the IBA field is always
clear.
FMTRAN
FF F954h
FSMTRAN
FF F754h
Flash Memory
Transition Time
Reload Register
FMPROG
FF F956h
FSMPROG
FF F756h
Flash Memory
Programming Time
Reload Register
FMPERASE
FF F958h
FSMPERASE
FF F758h
Flash Memory Page
Erase Time Reload
Register
FMMERASE0
FF F95Ah
FSMMERASE0
FF F75Ah
Flash Memory Module
Erase Time Reload
Register 0
FMEND
FF F95Eh
FSMEND
FF F75Eh
Flash Memory End
Time Reload Register
FMMEND
FF F960h
FSMMEND
FF F760h
Flash Memory Module
Erase End Time
Reload Register
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