CP3BT10 Datasheet, PDF (47/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

10.0 Interrupts
The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. Interrupts from the timers, UARTs, Microwire/
SPI interface, and Multi-Input Wake-Up are all maskable in-
terrupts. The highest-priority interrupt is the Non-Maskable
Interrupt (NMI), which is triggered by a falling edge received
on the NMI input pin.
The priorities of the maskable interrupts are hardwired and
therefore fixed. The interrupts are named IRQ0 through
IRQ31, in which IRQ0 has the lowest priority and IRQ31 has
the highest priority.
10.1 NON-MASKABLE INTERRUPTS
The Interrupt Control Unit (ICU) receives the external NMI
input and generates the NMI signal driven to the CPU. The
NMI input is an asynchronous input with Schmitt trigger
characteristics and an internal synchronization circuit,
therefore no external synchronizing circuit is needed. The
NMI pin triggers an exception on its falling edge.
10.1.1 Non-Maskable Interrupt Processing
The CPU performs an interrupt acknowledge bus cycle
when beginning to process a non-maskable interrupt. The
address associated with this core bus cycle is within the in-
ternal core address space and may be monitored as a Core
Bus Monitoring (CBM) clock cycle.
At reset, NMI interrupts are disabled and must remain dis-
abled until software initializes the interrupt table, interrupt
base register (INTBASE), and the interrupt mode. The ex-
ternal NMI interrupt is enabled by setting the EXNMI.EN-
LCK bit and will remain enabled until a reset occurs.
Alternatively, the external NMI interrupt can be enabled by
setting the EXNMI.EN bit and will remain enabled until an in-
terrupt event or a reset occurs.
10.2 MASKABLE INTERRUPTS
The ICU receives level-triggered interrupt request signals
from 31 internal sources and generates a vectored interrupt
to the CPU when required. Priority among the interrupt
sources (named IRQ1 through IRQ31) is fixed.
The maskable interrupts are globally enabled and disabled
by the E bit in the PSR register. The EI and DI instructions
are used to set (enable) and clear (disable) this bit. The glo-
bal maskable interrupt enable bit (I bit in the PSR) must also
be set before any maskable interrupts are taken.
Each interrupt source can be individually enabled or dis-
abled under software control through the ICU interrupt en-
able registers and also through interrupt enable bits in the
peripherals that request the interrupts. The CR16C core
supports IRQ0, but in the CP3BT10 it is not connected to
any interrupt source.
knowledge bus cycle on receiving a maskable interrupt re-
quest from the ICU. During the interrupt acknowledge cycle,
a byte is read from address FF FE00h (IVCT register). The
byte is used as an index into the Dispatch Table to deter-
mine the address of the interrupt handler.
Because IRQ0 is not connected to any interrupt source, it
would seem that the interrupt vector would never return the
value 10h. If it does return a value of 10h, the entry in the
dispatch table should point to a default interrupt handler that
handles this error condition. One possible condition for this
to occur is deassertion of the interrupt before the interrupt
acknowledge cycle.
10.3 INTERRUPT CONTROLLER REGISTERS
Table 21 lists the ICU registers.
Table 21 Interrupt Controller Registers
Name
NMISTAT
EXNMI
IVCT
IENAM0
IENAM1
ISTAT0
ISTAT1
Address
FF FE02h
FF FE04h
FF FE00h
FF FE0Eh
FF FE10h
FF FE0Ah
FF FE0Ch
Description
Non-Maskable Inter-
rupt Status Register
External NMI Trap
Control and Status
Register
Interrupt Vector
Register
Interrupt Enable and
Mask Register 0
Interrupt Enable and
Mask Register 1
Interrupt Status
Register 0
Interrupt Status
Register 1
10.3.1 Non-Maskable Interrupt Status Register
(NMISTAT)
The NMISTAT register is a byte-wide read-only register. It
holds the status of the current pending Non-Maskable Inter-
rupt (NMI) requests. On the CP3BT10, the external NMI in-
put is the only source of NMI interrupts. The NMISTAT
register is cleared on reset and each time its contents are
read.
7
1
0
Reserved
EXT
10.2.1 Maskable Interrupt Processing
Interrupt vector numbers are always positive, in the range ^EXT
10h to 2Fh. The IVCT register contains the interrupt vector
of the enabled and pending interrupt with the highest priori-
ty. The interrupt vector 10h corresponds to IRQ0 and the
lowest priority, while the vector 2Fh corresponds to IRQ31
and the highest priority. The CPU performs an interrupt ac-
The External NMI request bit indicates wheth-
er an external non-maskable interrupt request
has occurred. Refer to the description of the
EXNMI register below for additional details.
0 – No external NMI request.
1 – External NMI request has occurred.
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