CP3BT10 Datasheet, PDF (36/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

8.5.2 Flash Memory Information Block Data Register 8.5.4 Flash Memory 1 Write Enable Register
(FMIBDR/FSMIBDR)
(FM1WER)
The FMIBDR register holds the 16-bit data for read or write
access to an information block. The FMIBDR register is
cleared after device reset. The CPU bus master has read/
write access to this register.
15
0
IBD
The FM1WER register controls write protection for the sec-
ond half of the program flash memory. The data block is di-
vided into 16 8K-byte sections. Each bit in the FM1WER
register controls write protection for one of these sections.
The FM1WER register is cleared after device reset, so the
flash memory is write protected after reset. The CPU bus
master has read/write access to this registers.
15
0
IBD
The Information Block Data field holds the
FM1WE
data word for access to an information block.
For write operations the IBD field holds the
data word to be programmed into the informa- FM1WEn The Flash Memory 1 Write Enable n bits con-
tion block location specified by the IBA ad-
trol write protection for a section of a flash
dress. During a read operation from an
memory data block. The address mapping of
information block, the IBD field receives the
the register bits is shown below.
data word read from the location specified by
the IBA address.
Bit
Logical Address Range
8.5.3 Flash Memory 0 Write Enable Register
(FM0WER/FSM0WER)
The FM0WER register controls section-level write protec-
tion for the first half of the flash program memory. The
FMS0WER registers controls section-level write protection
for the flash data memory. Each data block is divided into 16
8K-byte sections. Each bit in the FM0WER and FSM0WER
registers controls write protection for one of these sections.
The FM0WER and FSM0WER registers are cleared after
device reset, so the flash memory is write protected after re-
set. The CPU bus master has read/write access to this reg-
isters.
15
0
FM0WE
0
1–14
15
02 0000h–02 1FFFh
...
03 E000h–03 FFFFh
8.5.5 Flash Data Memory 0 Write Enable Register
(FSM0WER)
The FSM0WER register controls write protection for the
flash data memory. The data block is divided into 16 512-
byte sections. Each bit in the FSM0WER register controls
write protection for one of these sections. The FSM0WER
register is cleared after device reset, so the flash memory is
write protected after reset. The CPU bus master has read/
write access to this registers.
FM0WEn
The Flash Memory 0 Write Enable n bits con-
trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
Bit
0
1–14
15
Logical Address Range
00 0000h–00 1FFFh
...
01 E000h–01 FFFFh
15
FSM0WEn
0
FSM0WE
The Flash Data Memory 0 Write Enable n bits
control write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
Bit
0
1–14
Logical Address Range
0E 0000h–0E 01FFh
...
15
0E 1E00h–0E 1FFFh
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