CP3BT10 Datasheet, PDF (52/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

11.1 EXTERNAL CRYSTAL NETWORK
An external crystal network is connected to the X1CKI and
X1CKO pins to generate the Main Clock, unless an external
clock signal is driven on the X1CKI pin. A similar external
crystal network may be used at pins X2CKI and X2CKO for
the Slow Clock. If an external crystal network is not used for
the Slow Clock, the Slow Clock is generated by dividing the
fast Main Clock.
crystal network and Table 24 shows the component specifi-
cations for the 32.768 kHz crystal network.
X1CKI/X2CKI
C1
The crystal network you choose may require external com-
ponents different from the ones specified in this datasheet.
In this case, consult with National’s engineers for the com-
ponent specifications
12 MHz/32.768 kHz
Crystal
X1CKO/X2CKO
The crystals and other oscillator components must be
placed close to the X1CKI/X1CKO and X2CKI/X2CKO de-
C2
vice input pins to keep the printed trace lengths to an abso-
lute minimum.
Figure 4 shows the required crystal network at X1CKI/
X1CKO and optional crystal network at X2CKI/X2CKO.
Table 23 shows the component specifications for the main
GND
DS007
Figure 4. External Crystal Network
Table 23 Component Values of the High Frequency Crystal Circuit
Component
Crystal
Capacitor C1, C2
Parameters
Resonance Frequency
Type
Max. Serial Resistance
Max. Shunt Capacitance
Load Capacitance
Capacitance
Values
12 MHz ± 20 ppm
AT-Cut
50 Ω
7 pF
22 pF
22 pF
Tolerance
N/A
20%
Table 24 Component Values of the Low Frequency Crystal Circuit
Component
Parameters
Values
Tolerance
Crystal
Capacitor C1, C2
Resonance Frequency
Type
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
Min. Q factor
Capacitance
32.768 kHz
Parallel
N-Cut or XY-bar
40 kΩ
2 pF
12.5 pF
40000
25 pF
N/A
20%
Choose capacitor component values in the tables to obtain
the specified load capacitance for the crystal when com-
bined with the parasitic capacitance of the trace, socket, and
package (which can vary from 0 to 8 pF). As a guideline, the
load capacitance is:
C2 > C1
CL = -^C----¹-----^×-----^C----²-- + Cparasitic
C1 + C2
C1 can be trimmed to obtain the desired load capacitance.
The start-up time of the 32.768 kHz oscillator can vary from
one to six seconds. The long start-up time is due to the high
Q value and high serial resistance of the crystal necessary
to minimize power consumption in Power Save mode.
11.2 MAIN CLOCK
The Main Clock is generated by the 12-MHz high-frequency
oscillator or driven by an external signal (typically the
LMX5252 RF chip). It can be stopped by the Power Man-
agement Module to reduce power consumption during peri-
ods of reduced activity. When the Main Clock is restarted, a
14-bit timer generates a Good Main Clock signal after a
start-up delay of 32,768 clock cycles. This signal is an indi-
cator that the high-frequency oscillator is stable.
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