CP3BT10 Datasheet, PDF (117/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

Table 44 Prescaler Factors (Continued)
In asynchronous mode, the baud rate is calculated by:
Prescaler Select
Prescaler Factor
11010
13.5
11011
14
11100
14.5
11101
15
11110
15.5
11111
16
A prescaler factor of zero corresponds to “no clock.” The “no
clock” condition is the UART power down mode, in which the
UART clock is turned off to reduce power consumption.
Software must select the “no clock” condition before enter-
ing a new baud rate. Otherwise, it could cause incorrect
data to be received or transmitted.
BR = ₍-^S--_O--^Y----_×-^S---_N-^_----^C-_×---^L--_P--^K---₎
where BR is the baud rate, SYS_CLK is the System Clock
frequency, O is the oversample rate, N is the value of the
baud rate divisor + 1, and P is the prescaler divide factor se-
lected by the value in the UPSR register.
19.2.6 Interrupts
The UART is capable of generating interrupts on:
„ Receive Buffer Full
„ Receive Error
„ Transmit Buffer Empty
Figure 46 shows a diagram of the interrupt sources and as-
sociated enable bits.
UFE
UDOE
UPE
UERR
UEEI
UERI
RX
Interrupt
URBF
UETI
UTBE
UEFCI
TX
Interrupt
UDCTS
FC
Interrupt
DS066
Figure 46. UART Interrupts
The interrupts can be individually enabled or disabled using
the Enable Transmit Interrupt (UETI), Enable Receive Inter-
rupt (UERI), and Enable Receive Error Interrupt (UEER)
bits in the UICTRL register.
A transmit interrupt is generated when both the UTBE and
UETI bits are set. To remove this interrupt, software must ei-
ther disable the interrupt by clearing the UETI bit or write to
the UTBUF register (which clears the UTBE bit).
A receive interrupt is generated on these conditions:
„ Both the URBF and UERI bits are set. To remove this in-
terrupt, software must either disable the interrupt by
clearing the UERI bit or read from the URBUF register
(which clears the URBF bit).
„ Both the UERR and the UEEI bits are set. To remove this
interrupt, software must either disable the interrupt by
clearing the UEEI bit or read the USTAT register (which
clears the UERR bit).
A flow control interrupt is generated when both the UDCTS
and the UEFCI bits are set. To remove this interrupt, soft-
ware must either disable the interrupt by clearing the UEFCI
bit or read the UICTRL register (which clears the UDCTS
bit).
In addition to the dedicated inputs to the ICU for UART in-
terrupts, the UART receive (RXD) and Clear To Send (CTS)
signals are inputs to the MIWU (see Section 13.0), which
can be programmed to generate edge-triggered interrupts.
19.2.7 DMA Support
The UART can operate with one or two DMA channels. Two
DMA channels must be used for processor-independent
full-duplex operation. Both receive and transmit DMA can
be enabled simultaneously.
If transmit DMA is enabled (the UETD bit is set), the UART
generates a DMA request when the UTBE bit changes state
from clear to set. Enabling transmit DMA automatically dis-
ables transmit interrupts, without regard to the state of the
UETI bit.
If receive DMA is enabled (the UERD bit is set), the UART
generates a DMA request when the URBF bit changes state
from clear to set. Enabling receive DMA automatically dis-
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