CP3BT10 Datasheet, PDF (29/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

6.4.5 Static Zone 2 Configuration Register (SZCFG2) 6.5
WAIT AND HOLD STATES
The SZCFG2 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL2 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
The number of wait cycles and hold cycles inserted into a
bus cycle depends on whether it is a read or write operation,
the type of memory or I/O being accessed, and the control
register settings.
6.5.1 Flash Program/Data Memory
7
6
5
BW WBR RBE
4
3
HOLD
2
0
WAIT
When the CPU accesses the Flash program and data mem-
ory (address ranges 000000h–03FFFFh and 0E0000h–
0E1FFFh), the number of added wait and hold cycles de-
pends on the type of access and the BIU register settings.
15
WAIT
HOLD
RBE
WBR
BW
FRE
IPST
IPRE
Reserved
12 11 10 9
8
FRE IPRE IPST Res.
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Memory Hold field specifies the number
of Thold clock cycles used for each memory
access, ranging from 00b for no Thold cycles
to 11b for three Thold clock cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG2.FRE bit is set or the
SZCFG2.BW is clear.
0 – Burst read disabled.
1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG2.FRE bit is set or
when SZCFG2.RBE is clear.
0 – No TBW on burst read cycles.
1 – One TBW on burst read cycles.
The Bus Width bit controls the bus width of the
zone.
0 – 8-bit bus width.
1 – 16-bit bus width.
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read op-
eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0 – Normal read cycles.
1 – Fast read cycles.
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone.
0 – No idle cycle.
1 – Idle cycle inserted.
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif-
ferent zone.
0 – No idle cycle.
1 – Idle cycle inserted.
In fast-read mode (SZCFG0.FRE=1), a read operation is a
single cycle access. This limits the maximum CPU operat-
ing frequency to 24 MHz.
For a read operation in normal-read mode
(SZCFG0.FRE=0), the number of inserted wait cycles is
specified in the SZCFG0.WAIT field. The total number of
wait cycles is the value in the WAIT field plus 1, so it can
range from 1 to 8. The number of inserted hold cycles is
specified in the SCCFG0.HOLD field, which can range from
0 to 3.
For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is 1. No hold cycles are
used.
For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in
the early write mode). The number of inserted hold cycles is
equal to the value written to the SCCFG0.HOLD field, which
can range from 0 to 3.
6.5.2 RAM Memory
Read and write accesses to on-chip RAM is performed with-
in a single cycle, without regard to the BIU settings. The
RAM address is in the range of 0E 8000h–0E 91FFh and 0E
C000h–0E EBFFh.
6.5.3 Access to Peripherals
When the CPU accesses on-chip peripherals in the range of
0E F000h–0E F1FFh and FF 0000h–FF FBFFh, one wait
cycle and one preliminary idle cycle is used. No hold cycles
are used. The IOCFG register determines the access timing
for the address range FF FB00h–FF FBFFh.
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