CP3BT10 Datasheet, PDF (127/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

MSK
Shift
Out
End of Transfer
Data Out
Data In
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Bit 0
(LSB)
Bit 0
(LSB)
DS072
Figure 52. Alternate Mode (SCIDL = 1)
20.3 SLAVE MODE
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO is placed in TRI-STATE mode when MWCS is
inactive. Data transfer is enabled when MWCS is active.
Figure 53 illustrates the various interrupt capabilities of this
module.
EIO
The slave starts driving MDIDO when MWCS is activated.
The most significant bit (lower byte in 8-bit mode or upper
byte in 16-bit mode) is output onto the MDIDO pin first. After
eight or sixteen clocks (depending on the selected mode),
the data transfer is completed.
OVR = 1
EIR
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the
“Echo Enable” (ECHO) bit is set, the data received from
MDODI is transmitted on MDIDO in addition to being shifted
to MWDAT. If the ECHO bit is clear, the data transmitted on
MDIDO is the data held in the MWDAT register, regardless
of its validity. The master may negate the MWCS signal to
synchronize the bit count between the master and the slave.
In the case that the slave is the only slave in the system,
MWCS can be tied to VSS.
20.4 INTERRUPT GENERATION
An interrupt is generated in any of the following cases:
„ When the read buffer is full (RBF = 1) and the “Enable In-
terrupt for Read” bit is set (EIR = 1).
„ Whenever the shifter is not busy, i.e. the BSY bit is clear
(BSY = 0) and the “Enable Interrupt for Write” bit is set
(EIW = 1).
„ When an overrun condition occurs (OVR is set) and the
“Enable Interrupt on Overrun” bit is set (MEIO = 1). This
usage is restricted to master mode.
In addition, MWCS is an input to the MIWU (see
Section 13.0), which can be programmed to generate an
edge-triggered interrupt.
RBF = 1
EIW
MWSPI
Interrupt
BSY = 0
DS073
Figure 53. MWSPI Interrupts
20.5 MICROWIRE INTERFACE REGISTERS
Software interacts with the Microwire interface by accessing
the Microwire registers. There are three such registers:
Table 48 Microwire Interface Registers
Name
MWDAT
MWCTL1
MWSTAT
Address
FF FE60h
FF FE62h
FF FE64h
Description
Microwire Data
Register
Microwire Control
Register
Microwire Status
Register
20.5.1 Microwire Data Register (MWDAT)
The MWDAT register is a word-wide, read/write register
used to transmit and receive data through the MDODI and
MDIDO pins. Figure 54 shows the hardware structure of the
register.
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