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CP3BT10 Datasheet, PDF (14/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces
Name Pins I/O
Primary Function
Alternate
Name
Alternate Function
RD
ENV0
ENV1
ENV2
1 Output External Memory Read
None
None
1 I/O
Special mode select input with in-
ternal pull-up during reset
PLLCLK
PLL Clock Output
1 I/O
Special mode select input with in-
ternal pull-up during reset
CPUCLK
CPU Clock Output
1 I/O
Special mode select input with in-
ternal pull-up during reset
SLOWCLK
Slow Clock Output
Table 5 CP3BT10 Pin Descriptions for the 48-Pin CSP
Name Pins I/O
Primary Function
Alternate
Name
Alternate Function
X1CKI
X1CKO
X2CKI
X2CKO
AVCC
IOVCC
VCC
GND
AGND
RESET
TMS
TDI
TDO
TCK
RDY
PG0
1 Input 12 MHz Oscillator Input
1 Output 12 MHz Oscillator Output
1 Input 32 kHz Oscillator Input
1 Output 32 kHz Oscillator Output
1 Input PLL Analog Power Supply
2 Input 2.5V - 3.3V I/O Power Supply
2 Input
2.5V Core Logic
Power Supply
4 Input Reference Ground
1 Input PLL Analog Ground
1 Input Chip general reset
1 Input
JTAG Test Mode Select
(with internal weak pull-up)
1 Input
JTAG Test Data Input
(with internal weak pull-up)
1 Output JTAG Test Data Output
1 Input
JTAG Test Clock Input
(with internal weak pull-up)
1 Output NEXUS Ready Output
1 I/O
Generic I/O
PG1
1 I/O
Generic I/O
PG2
1 I/O
Generic I/O
PG3
1 I/O
Generic I/O
PG5
1 I/O
Generic I/O
BBCLK
None
None
None
None
None
None
None
None
None
None
None
None
None
None
RXD
WUI10
TXD
WUI11
RTS
WUI12
CTS
WUI13
SRFS
NMI
BB reference clock for the RF Interface
None
None
None
None
None
None
None
None
None
None
None
None
None
None
UART Receive Data Input
Multi-Input Wake-Up Channel 10
UART Transmit Data Output
Multi-Input Wake-Up Channel 11
UART Ready-To-Send Output
Multi-Input Wake-Up Channel 12
UART Clear-To-Send Input
Multi-Input Wake-Up Channel 13
AAI Receive Frame Sync
Non-Maskable Interrupt Input
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