CP3BT10 Datasheet, PDF (190/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

27.9 MICROWIRE/SPI TIMING
Table 61 Microwire/SPI Signals
Symbol Figure
Description
Reference
Microwire/SPI Input Signals
t_MSKh
t_MSKl
t_MSKp
t_MSKh
t_MSKs
t_MCSh
t_MCSs
t_MDIh
t_MDIs
81 Microwire Clock High
At 2.0V (both edges)
81 Microwire Clock Low
At 0.8V (both edges)
81
Microwire Clock Period
82
SCIDL bit = 0; Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1; Falling Edge
(FE) MSK to next FE MSK
81 MSK Hold (slave only)
After MWCS goes inactive
81 MSK Setup (slave only)
Before MWCS goes active
81
MWCS Hold (slave only)
82
SCIDL bit = 0; After FE
MSK
SCIDL bit = 1; After RE
MSK
81
MWCS Setup (slave only)
82
SCIDL bit = 0; Before RE
MSK
SCIDL bit = 1; Before FE
MSK
81
Microwire Data In Hold (master)
83
Normal Mode; After RE
MSK
Alternate Mode; After FE
MSK
81
Microwire Data In Hold (slave)
83
Normal Mode; After RE
MSK
Alternate Mode; After FE
MSK
81
Microwire Data In Setup
83
Normal Mode; Before RE
MSK
Alternate Mode; Before FE
MSK
Microwire/SPI Output Signals
t_MSKh
t_MSKl
t_MSKp
t_MSKd
t_MDOf
t_MDOh
t_MDOnf
81 Microwire Clock High
At 2.0V (both edges)
81 Microwire Clock Low
At 0.8V (both edges)
81
Microwire Clock Period
82
SCIDL bit = 0: Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1: Falling Edge
(FE) MSK to next FE MSK
81
MSK Leading Edge Delayed (master
only)
Data Out Bit #7 Valid
81
Microwire Data Float ^b
(slave only)
After RE on MCSn
81
Microwire Data Out Hold
82
Normal Mode; After FE
MSK
Alternate Mode; After RE
MSK
85 Microwire Data No Float (slave only) After FE on MWCS
Min (ns)
80
80
200
40
80
40
80
0
40
80
40
40
100
0.5 t_MSK
-
0.0
0
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Max (ns)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5 t_MSK
25
-
25