CP3BT10 Datasheet, PDF (150/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

23.5.5 Reload/Capture A Register (TCRA)
The TCRA register is a word-wide, read/write register that
holds the reload or capture value for Timer/Counter 1. The
register contents are not affected by a reset and are un-
known after power-up.
15
0
TCRA
23.5.6 Reload B Register (TCRB)
The TCRB register is a word-wide, read/write register that
holds the reload value for Timer/Counter 2. The register
contents are not affected by a reset and are unknown after
power-up.
15
0
TCRB
23.5.7 Timer Mode Control Register (TCTRL)
The TCTRL register is a byte-wide, read/write register that
sets the operating mode of the timer/counter and the TA pin.
This register is cleared at reset. The register format is
shown below.
7
6
5
4
3
2 10
TEN TAOUT Res. TAEN Res. TAEDG MDSEL
MDSEL
TAEDG
The Mode Select field sets the operating
mode of the timer/counter as follows:
00 – Mode 1: PWM plus system timer.
01 – Mode 2: Input Capture plus system tim-
er.
10 – Mode 3: Dual Timer/Counter.
11 – Reserved.
The TA Edge Polarity bit selects the polarity of
the edges that trigger the TA input.
0 – TA input is sensitive to falling edges (high
to low transitions).
1 – TA input is sensitive to rising edges (low
to high transitions).
TAEN
TAOUT
TEN
The TA Enable bit controls whether the TA pin
is enabled to operate as a preset input or as a
PWM output, depending on the timer operat-
ing mode. In Mode 2 (Dual Input Capture), a
transition on the TA pin presets the TCNT1
counter to FFFFh. In the other modes, TA
functions as a PWM output. When this bit is
clear, operation of the pin for the timer/counter
is disabled.
0 – TA input disabled.
1 – TA input enabled.
The TA Output Data bit indicates the current
state of the TA pin when the pin is used as a
PWM output. The hardware sets and clears
this bit, but software can also read or write this
bit at any time and therefore control the state
of the output pin. In case of conflict, a software
write has precedence over a hardware up-
date. This bit setting has no effect when the
TA pin is used as an input.
0 – TA pin is low.
1 – TA pin is high.
The Timer Enable bit controls whether the
Multi-Function Timer is enabled. When the
module is disabled all clocks to the counter
unit are stopped to minimize power consump-
tion. For that reason, the timer/counter regis-
ters (TCNT1 and TCNT2), the capture/reload
registers (TCRA and TCRB), and the interrupt
pending bits (TXPND) cannot be written in
this mode. Also, the 5-bit clock prescaler and
the interrupt pending bits are cleared, and the
TA I/O pin becomes an input.
0 – Multi-Function Timer is disabled.
1 – Multi-Function Timer is enabled.
23.5.8 Timer Interrupt Control Register (TICTL)
The TICTL register is a byte-wide, read/write register that
contains the interrupt enable bits and interrupt pending bits
for the four timer interrupt sources, designated A, B, C, and
D. The condition that causes each type of interrupt depends
on the operating mode, as shown in Table 51.
This register is cleared upon reset. The register format is
shown below.
7
6
54
3
2
1
0
TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND
TAPND
The Timer Interrupt Source A Pending bit indi-
cates that timer interrupt condition A has oc-
curred. For an explanation of interrupt
conditions A, B, C, and D, see Table 51. This
bit can be set by hardware or by software. To
clear this bit, software must use the Timer In-
terrupt Clear Register (TICLR). Any attempt
by software to directly write a 0 to this bit is ig-
nored.
0 – Interrupt source A has not triggered.
1 – Interrupt source A has triggered.
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