CP3BT10 Datasheet, PDF (200/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

27.14 EXTERNAL BUS TIMING
Table 66 External Bus Signals
Symbol Figure
Description
Reference
External Bus Input Signals
t₁
92,
94,
95, 96
Input Setup Time
D[15:0]
t₂
92,
94,
95, 96
Output Hold Time
D[15:0]
Before Rising Edge (RE)
on CLK
After RE on CLK
External Bus Output Signals
t₃
92, 93
Output Valid Time
D[15:0]
t₄
92,
93,
94,
95, 96
Output Valid Time
A[21:0] (CP3BT10)
A[22:0] (CP3BT13)
92, Output Active/Inactive Time
t₅
93, RD
94, SEL[1:0]
95, 96 SELIO
t₆
92, 93
Output Active/Inactive Time
WR[1:0]
t₇
94
Minimum Inactive Time
RD
t₈
92
Output Float Time
D[15:0]
t₉
92 Minimum Delay Time
t₁₀ 92, 93 Minimum Delay Time
t₁₁
93 Minimum Delay Time
Output Hold Time
t₁₂
92,
93,
94,
95, 96
A22 (CP3BT13 only)
A[21:0]
D[15:0]
RD
SEL[2:0]
SELIO
t₁₃
92, 93
Output Hold Time
WR[1:0]
After RE on CLK
After RE on CLK
After RE on CLK
After RE on CLK
At 2.0V
After RE on CLK
From RD Trailing Edge
(TE) to D[15:0] driven
From RD TE to SELn
Leading Edge (LE)
From SELx TE to SELy LE
After RE on CLK
After RE on CLK
Min (ns)
8
0
-
-
-
-
Tclk - 4
-
Tclk - 4
0
0
0
0.5 Tclk - 3
Max (ns)
-
-
8
8
8
0.5 Tclk + 8
-
8
-
-
-
-
-
www.national.com
200