CP3BT10 Datasheet, PDF (62/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

Peripheral BUS
WUI0
WUI15
WKEDG
15 ^{. . . . . . . . . . .} 0
WKIENA
WKICTL 1-2
0
15
WKPND
4
Encoder
EXINT3:0 to ICU
Wake-Up Signal
To Power Mgt
WKENA
15 ^{. . . . . . . . . . .} 0
DS009
Figure 10. Multi-Input Wake-Up Module Block Diagram
13.1.2 Wake-Up Enable Register (WKENA)
The Wake-Up Enable (WKENA) register is a word-wide
read/write register that individually enables or disables
wake-up events from the MIWU channels. The WKENA reg-
ister is cleared upon reset, which disables all wake-up/inter-
rupt channels. The register format is shown below.
13.1.4 Wake-Up Interrupt Control Register 1
(WKICTL1)
The WKICTL1 register is a word-wide read/write register
that selects the interrupt request signal for the associated
MIWU channels WUI7:0. At reset, the WKICTL1 register is
cleared, which selects MIWU Interrupt Request 0 for all
eight channels. The register format is shown below.
15
0
WKEN
WKEN
The Wake-Up Enable bits enable and disable
the MIWU channels. The WKEN15:0 bits cor-
respond to the WUI15:0 channels, respective-
ly.
0 – MIWU channel wake-up events disabled.
1 – MIWU channel wake-up events enabled.
13.1.3 Wake-Up Interrupt Enable Register (WKIENA)
The WKIENA register is a word-wide read/write register that
enables and disables interrupts from the MIWU channels.
The register format is shown below.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN
TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
WKINTR
The Wake-Up Interrupt Request Select fields
select which of the four MIWU interrupt re-
quests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 0.
01 – Selects MIWU interrupt request 1.
10 – Selects MIWU interrupt request 2.
11 – Selects MIWU interrupt request 3.
15
0
WKIEN
WKIEN
The Wake-Up Interrupt Enable bits control
whether MIWU channels generate interrupts.
0 – Interrupt disabled.
1 – Interrupt enabled.
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