CP3BT10 Datasheet, PDF (33/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

4. Write to an address within the desired page.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit to confirm successful
erase of the page. The EERR bit is in the FMSTAT or
FSMSTAT register.
7. Repeat steps 4 through 6 to erase additional pages.
8. Clear the PER bit.
8.3.4 Main Block Module Erase
A module erase operation can be used to erase an entire
main block. All sections within the block must be enabled for
writing. If a boot area is defined in the block, it cannot be
erased. The following steps are performed to erase a main
block:
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while erasing is
in progress.
3. Set the Module Erase (MER) bit. The MER bit is in the
FMCTRL or FSMCTRL register.
4. Write to any address within the desired main block.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit to confirm successful
erase of the block. The EERR bit is in the FMSTAT or
FSMSTAT register.
7. Clear the MER bit.
8.3.5 Information Block Module Erase
Erasing an information block also erases the corresponding
main block. If a boot area is defined in the main block, nei-
ther block can be erased. Page erase is not supported for
information blocks. The following steps are performed to
erase an information block:
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while erasing is
in progress.
3. Set the Module Erase (MER) bit. The MER bit is in the
FMCTRL or FSMCTRL register.
4. Load the FMIBAR or FSMIBAR register with any ad-
dress within the block, then write any data to the FMIB-
DR or FSMIBDR register.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit to confirm successful
erase of the block. The EERR bit is in the FMSTAT or
FSMSTAT register.
7. Clear the MER bit.
8.3.6 Main Block Write
Writing is only allowed when global write protection is dis-
abled. Writing by the CPU is only allowed when the write en-
able bit is set for the sector which contains the word to be
written. The CPU cannot write the Boot Area. Only word-
wide write access to word-aligned addresses is supported.
The following steps are performed to write a word:
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while the write
is in progress.
3. Set the Program Enable (PE) bit. The PE bit is in the
FMCTRL or FSMCTRL register.
4. Write a word to the desired word-aligned address. This
starts a new pipelined programming sequence. The
FMBUSY bit becomes set while the write operation is in
progress. The FMFULL bit in the FMSTAT or FSMSTAT
register becomes set if a previous write operation is still
in progress.
5. Wait until the FMFULL bit becomes clear.
6. Repeat steps 4 and 5 for additional words.
7. Wait until the FMBUSY bit becomes clear again.
8. Check the programming error (PERR) bit to confirm
successful programming. The PERR bit is in the FM-
STAT or FSMSTAT register.
9. Clear the Program Enable (PE) bit.
8.3.7 Information Block Write
Writing is only allowed when global write protection is dis-
abled. Writing by the CPU is only allowed when the write en-
able bit is set for the sector which contains the word to be
written. The CPU cannot write Information Block 0. Only
word-wide write access to word-aligned addresses is sup-
ported. The following steps are performed to write a word:
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while the write
is in progress.
3. Set the Program Enable (PE) bit. The PE bit is in the
FMCTRL or FSMCTRL register.
4. Write the desired target address into the FMIBAR or
FSMIBAR register.
5. Write the data word into the FMIBDR or FSMIBDR reg-
ister. This starts a new pipelined programming se-
quence. The FMBUSY bit becomes set while the write
operation is in progress. The FMFULL bit in the FM-
STAT or FSMSTAT register becomes set if a previous
write operation is still in progress.
6. Wait until the FMFULL bit becomes clear.
7. Repeat steps 4 through 6 for additional words.
8. Wait until the FMBUSY bit becomes clear again.
9. Check the programming error (PERR) bit to confirm
successful programming. The PERR bit is in the FM-
STAT or FSMSTAT register.
10. Clear the Program Enable (PE) bit.
8.4 INFORMATION BLOCK WORDS
Two words in the information blocks are dedicated to hold
settings that affect the operation of the system: the Function
Word in Information Block 0 and the Protection Word in In-
formation Block 1.
8.4.1 Function Word
The Function Word resides in the Information Block 0 at ad-
dress 07Eh. At reset, the Function Word is copied into the
FMAR0 register.
15
Reserved
1
0
USB_ENABLE
33
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