CP3BT10 Datasheet, PDF (155/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

Figure 70 illustrates the configuration of a timer subsystem
while operating in capture mode. The numbering in
Figure 70 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
7
0
C1PRSC
==
Prescaler
Counter
TMOD1=11
24.1.5 Interrupts
The VTU has a total of 16 interrupt sources, four for each of
the four timer subsystems. All interrupt sources have a
pending bit and an enable bit associated with them. All in-
terrupt pending bits are denoted IxAPD through IxDPD
where “x” relates to the specific timer subsystem. There is
one system level interrupt request for each of the four timer
subsystems.
Figure 71 illustrates the interrupt structure of the versatile
timer module.
T1RUN
15
Restart
Count1[15:0]
0
15:0
I1AEN
I1BEN
I1CEN
Compare
I1DEN
PERCAP1[15:0]
Compare
I1APD
I1BPD
System
Interrupt
Request 1
DTYCAP1[15:0]
I1CPD
I1DPD
cap
cap
rst
rst
2
0
C1EDG
TIO1
2
0
C2EDG
TIO2
DS092
I4AEN
I4BEN
I4CEN
I4DEN
Figure 70. VTU Dual 16-bit Capture Mode
24.1.4 Low Power Mode
I4APD
I4BPD
System
Interrupt
Request 4
In case a timer subsystem is not used, software can place it
in a low-power mode. All clocks to a timer subsystem are
stopped and the counter and prescaler contents are frozen
once low-power mode is entered. Software may continue to
write to the MODE, INTCTL, IOxCTL, and CLKxPS regis-
ters. Write operations to the INTPND register are allowed;
but if a timer subsystem is in low-power mode, its associat-
ed interrupt pending bits cannot be cleared. Software can-
not write to the COUNTx, PERCAPx, and DTYCAPx
registers of a timer subsystem while it is in low-power mode.
All registers can be read at any time.
I4CPD
I4DPD
DS093
Figure 71. VTU Interrupt Request Structure
Each of the timer pending bits - IxAPD through IxDPD - is
set by a specific hardware event depending on the mode of
operation, i.e., PWM or Capture mode. Table 54 outlines the
specific hardware events relative to the operation mode
which cause an interrupt pending bit to be set.
Table 54 VTU Interrupt Sources
Pending Flag
Dual 8-bit PWM Mode
16-bit PWM Mode
Capture Mode
IxAPD
IxBPD
IxCPD
IxDPD
Low Byte Duty Cycle match
Low Byte Period match
High Byte Duty Cycle match
High Byte Period match
Duty Cycle match
Period match
N/A
N/A
Capture to PERCAPx
Capture to DTYCAPx
Counter Overflow
N/A
24.1.6 ISE Mode operation
The VTU supports breakpoint operation of the In-System-
Emulator (ISE). If FREEZE is asserted, all timer counter
clocks will be inhibited and the current value of the timer reg-
isters will be frozen; in capture mode, all further capture
events are disabled. Once FREEZE becomes inactive,
counting will resume from the previous value and the cap-
ture input events are re-enabled.
155
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