CP3BT10 Datasheet, PDF (24/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

Mnemonic
STORMP
imm3
DI
EI
EIWAIT
NOP
WAIT
Table 7 Instruction Set Summary
Operands
Description
Store 1 to 8 registers (R2-R5, R8-R11) to memory starting
at (R7,R6)
Disable maskable interrupts
Enable maskable interrupts
Enable maskable interrupts and wait for interrupt
No operation
Wait for interrupt
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