CP3BT10 Datasheet, PDF (149/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

23.5 TIMER REGISTERS
Table 53 lists the CPU-accessible registers used to control
the Multi-Function Timers.
Table 53 Multi-Function Timer Registers
Name
Address
Description
23.5.2 Clock Unit Control Register (TCKC)
The TCKC register is a byte-wide, read/write register that
selects the clock source for each timer/counter. Selecting
the clock source also starts the counter. This register is
cleared on reset, which disables the timer/counters. The
register format is shown below.
TPRSC
TCKC
TCNT1
TCNT2
TCRA
TCRB
TCTRL
TICTL
TICLR
FF FF48h
FF FF4Ah
FF FF40h
FF FF46h
FF FF42h
FF FF44h
FF FF4Ch
FF FF4Eh
FF FF50h
Clock Prescaler
Register
Clock Unit Control
Register
Timer/Counter 1
Register
Timer/Counter 2
Register
Reload/Capture A
Register
Reload/Capture B
Register
Timer Mode
Control Register
Timer Interrupt
Control Register
Timer Interrupt
Clear Register
23.5.1 Clock Prescaler Register (TPRSC)
The TPRSC register is a byte-wide, read/write register that
holds the current value of the 5-bit clock prescaler (CLKPS).
This register is cleared on reset. The register format is
shown below.
7
6
Reserved
5
3
C2CSEL
2
0
C1CSEL
C1CSEL
C2CSEL
The Counter 1 Clock Select field specifies the
clock mode for Timer/Counter 1 as follows:
000 – No clock (Timer/Counter 1 stopped,
modes 1, 2, and 3 only).
001 – Prescaled System Clock.
010 – Reserved.
011 – Reserved.
100 – Slow Clock.*
101 – Reserved.
110 – Reserved.
111 – Reserved.
The Counter 2 Clock Select field specifies the
clock mode for Timer/Counter 2 as follows:
000 – No clock (Timer/Counter 2 stopped,
modes 1, 2, and 3 only).
001 – Prescaled System Clock.
010 – Reserved.
011 – Reserved.
100 – Slow Clock*
101 – Reserved.
110 – Reserved.
111 – Reserved.
* Operation of the Slow Clock is determined by the CRC-
TRL.SCLK control bit, as described in Section 11.8.1.
23.5.3 Timer/Counter 1 Register (TCNT1)
7
5
4
Reserved
CLKPS
0
The TCNT1 register is a word-wide, read/write register that
holds the current count value for Timer/Counter 1. The reg-
ister contents are not affected by a reset and are unknown
after power-up.
CLKPS
The Clock Prescaler field specifies the divisor
used to generate the Timer Clock from the
System Clock. When the timer is configured to
use the prescaled clock, the System Clock is
divided by (CLKPS + 1) to produce the timer
clock. Therefore, the System Clock divisor
can range from 1 to 32.
15
0
TCNT1
23.5.4 Timer/Counter 2 Register (TCNT2)
The TCNT2 register is a word-wide, read/write register that
holds the current count value for Timer/Counter 2. The reg-
ister contents are not affected by a reset and are unknown
after power-up.
15
0
TCNT2
149
www.national.com