CP3BT10 Datasheet, PDF (195/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

27.10 ACCESS.BUS TIMING
Table 62 ACCESS.bus Signals
Symbol Figure
Description
Reference
ACCESS.bus Input Signals
t_BUFi
87
Bus free time between Stop and Start
Condition
t_CSTOsi
t_CSTRhi
t_CSTRsi
t_DHCsi
87 SCL setup time
87 SCL hold time
87 SCL setup time
88 Data High setup time
Before Stop Condition
After Start Condition
Before Start Condition
Before SCL Rising Edge
(RE)
t_DLCsi
t_SCLfi
t_SCLri
t_SCLlowi
87 Data Low setup time
86 SCL signal Rise time
86 SCL signal Fall time
89 SCL low time
Before SCL RE
After SCL Falling Edge
(FE)
t_SCLhighi 89 SCL high time
t_SDAfl
86 SDA signal Fall time
t_SDAri
86 SDA signal Rise time
t_SDAhi
89 SDA hold time
t_SDAsi
89 SDA setup time
After SCL RE
After SCL FE
Before SCL RE
ACCESS.bus Output Signals
t_BUFo
t_CSTOso
t_CSTRho
t_CSTRso
t_DHCso
t_DLCso
t_SCLfo
t_SCLro
t_SCLlowo
t_SCLhigh
o
t_SDAfo
t_SDAro
t_SDAho
t_SDAvo
87 _{Bus free time between Stop and Start}
Condition
87 SCL setup time
Before Stop Condition
87 SCL hold time
After Start Condition
88 SCL setup time
Before Start Condition
88 Data High setup time
Before SCL R.E.
87 Data Low setup time
Before SCL R.E.
86 SCL signal Fall time
86 SCL signal Rise time
89 SCL low time
After SCL F.E.
89 SCL high time
After SCL R.E.
86 _{SDA signal Fall time}
86 _{SDA signal Rise time}
89 SDA hold time
89 SDA valid time
After SCL F.E.
After SCL F.E.
Min (ns)
Max (ns)
t_SCLhigho
(8 × t_CLK) - t_SCLri
(8 × t_CLK) - t_SCLri
(8 × t_CLK) - t_SCLri
2 × t_CLK
2 × t_CLK
-
-
16 × t_CLK
16 × t_CLK
-
-
0
2 × t_CLK
-
-
-
-
-
-
300
1000
-
-
300
1000
-
-
t_SCLhigho
-
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho -t_SDAro
t_SCLhigho -t_SDAfo
-
-
(K × t_CLK) -1^e
(K × t_CLK) -1^e
-
-
-
-
-
300 ^c
-^d
-
-
-
300
-
-
(7 × t_CLK) - t_SCLfo
-
-
(7 × t_CLK) + t_RD
195
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