CP3BT10 Datasheet, PDF (126/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

the normal and the alternate modes with the SCIDL bit
equal to 0 and equal to 1.
Note that when data is shifted out on MDODI (master mode)
or MDIDO (slave mode) on the leading edge of the MSK
clock, bit 14 (16-bit mode) is shifted out on the second lead-
ing edge of the MSK clock. When data are shifted out on
MDODI (master mode) or MDIDO (slave mode) on the trail-
ing edge of MSK, bit 14 (16-bit mode) is shifted out on the
first trailing edge of MSK.
20.2 MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the (MWDAT register), eight
or sixteen MSK clocks, depending on the mode selected,
are generated to shift the 8 or 16 bits of data and then MSK
goes idle again. The MSK idle state can be either high or
low, depending on the SCIDL bit.
MSK
Data Out
Data In
Shift
Out
MSB
MSB - 1
Sample
Point
MSB
MSB - 1
MSB - 2
MSB - 2
End of Transfer
Bit 1
Bit 1
Bit 0
(LSB)
Bit 0
(LSB)
DS069
Figure 49. Normal Mode (SCIDL = 0)
MSK
Data Out
Data In
Shift
Out
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Figure 50. Normal Mode (SCIDL = 1)
End of Transfer
Bit 0
(LSB)
Bit 0
(LSB)
DS070
MSK
Data Out
Data In
Shift
Out
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Figure 51. Alternate Mode (SCIDL = 0)
End of Transfer
Bit 0
(LSB)
Bit 0
(LSB)
DS071
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