CP3BT10 Datasheet, PDF (112/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

18.9.5 Logarithmic PCM Data Input Register (LOGIN)
The LOGIN register is an 8-bit wide write-only register. It is
used to receive 8-bit logarithmic PCM data from the periph-
eral bus and convert it into 13-bit linear PCM data.
7
0
LOGIN
18.9.6 Logarithmic PCM Data Output Register
(LOGOUT)
The LOGOUT register is an 8-bit wide read-only register. It
holds logarithmic PCM data that has been converted from
linear PCM data. After reset, the LOGOUT register is clear.
7
0
LOGOUT
18.9.7 Linear PCM Data Input Register (LINEARIN)
The LINEARIN register is a 16-bit wide write-only register.
The data is left-aligned. When converting to A-law, bits 2:0
are ignored. When converting to µ-law, bits 1:0 are ignored.
15
0
LINEARIN
18.9.8 Linear PCM Data Output Register
(LINEAROUT)
The LINEAROUT register is a 16-bit wide read-only register.
The data is left-aligned. When converting from A-law, bits
2:0 are clear. When converting from µ-law, bits 1:0 are clear.
After reset, this register is clear.
15
0
LINEAROUT
18.9.9 CVSD Control Register (CVCTRL)
The CVCTRL register is a 16-bit wide, read/write register
that controls the mode of operation and of the module’s in-
terrupts. At reset, all implemented bits are cleared.
7
DMA
PO
6
DMA
CI
5
4
3
2
DMA
CO
CVSD
ERR-
INT
CVSD
INT
PCM
INT
1
0
CLK
EN
CVEN
15 14 13 12
11
10 9
8
Res. RESOLUTION PCMCONV CVSDCONV DMAPI
CVEN
CLKEN
PCMINT
CVSDINT
CVSDERRINT
DMACO
DMACI
DMAPO
The Module Enable bit enables or disables the
CVSD conversion module interface. When the
bit is set, the interface is enabled which allows
read and write operations to the rest of the
module. When the bit is clear, the module is
disabled. When the module is disabled the
status register CVSTAT will be cleared to its
reset state.
0 – CVSD module enabled.
1 – CVSD module disabled.
The CVSD Clock Enable bit enables the 2-
MHz clock to the filter engine and CVSD en-
coders and decoders.
0 – CVSD module clock disabled.
1 – CVSD module clock enabled.
The PCM Interrupt Enable bit controls gener-
ation of the PCM interrupt. If set, this bit en-
ables the PCM interrupt. If the PCMINT bit is
clear, the PCM interrupt is disabled. After re-
set, this bit is clear.
0 – PCM interrupt disabled.
1 – PCM interrupt enabled.
The CVSD FIFO Interrupt Enable bit controls
generation of the CVSD interrupt. If set, this
bit enables the CVSD interrupt that occurs if
the CVSD In FIFO is nearly empty or the
CVSD Out FIFO is nearly full. If the CVSDINT
bit is clear, the CVSD nearly full/nearly empty
interrupt is disabled. After reset, this bit is
clear.
0 – CVSD interrupt disabled.
1 – CVSD interrupt enabled.
The CVSD FIFO Error Interrupt Enable bit
controls generation of the CVSD error inter-
rupt. If set, this bit enables an interrupt to oc-
cur when the CVSD Out FIFO is full or the
CVSD In FIFO is empty. If the CVSDERROR-
INT bit is clear, the CVSD full/empty interrupt
is disabled. After reset, this bit is clear.
0 – CVSD error interrupt disabled.
1 – CVSD error interrupt enabled.
The DMA Enable for CVSD Out bit enables
hardware DMA control for reading CVSD data
from the CVSD Out FIFO. If clear, DMA sup-
port is disabled. After reset, this bit is clear.
0 – CVSD output DMA disabled.
1 – CVSD output DMA enabled.
The DMA Enable for CVSD In bit enables
hardware DMA control for writing CVSD data
into the CVSD In FIFO. If clear, DMA support
is disabled. After reset, this bit is clear.
0 – CVSD input DMA disabled.
1 – CVSD input DMA enabled.
The DMA Enable for PCM Out bit enables
hardware DMA control for reading PCM data
from the PCMOUT register. If clear, DMA sup-
port is disabled. After reset, this bit is clear.
0 – PCM output DMA disabled.
1 – PCM output DMA enabled.
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