CP3BT10 Datasheet, PDF (118/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

ables receive interrupts, without regard to the state of the
UERI bit. However, receive error interrupts should be en-
abled (the UEEI bit is set) to allow detection of receive errors
when DMA is used.
19.3.1 UART Receive Data Buffer (URBUF)
The URBUF register is a byte-wide, read/write register used
to receive each data byte.
19.2.8 Break Generation and Detection
A line break is generated when the UBRK bit is set in the
UMDSL1 register. The TXD line remains low until the pro-
gram resets the UBRK bit.
A line break is detected if RXD remains low for 10 bit times
or longer after a missing stop bit is detected.
19.2.9 Parity Generation and Detection
7
0
URBUF
19.3.2 UART Transmit Data Buffer (UTBUF)
The UTBUF register is a byte-wide, read/write register used
to transmit each data byte.
Parity is only generated or checked with the 7-bit and 8-bit
data formats. It is not generated or checked in the diagnostic
loopback mode, the attention mode, or in normal mode with
the 9-bit data format. Parity generation and checking are en-
abled and disabled using the PEN bit in the UFRS register.
The UPSEL bits in the UFRS register are used to select
odd, even, or no parity.
19.3 UART REGISTERS
Software interacts with the UART by accessing the UART
registers. There are eight registers, as listed in Table 45.
7
0
UTBUF
19.3.3 UART Baud Rate Prescaler (UPSR)
The UPSR register is a byte-wide, read/write register that
contains the 5-bit clock prescaler and the upper three bits of
the baud rate divisor. This register is cleared upon reset.
The register format is shown below.
Table 45 UART Registers
7
3
2
0
Name
Address
Description
UPSC
UDIV10:8
URBUF
UTBUF
UPSR
UBAUD
UFRS
UMDSL1
USTAT
UICTRL
FF FE42h
FF FE40h
FF FE4Eh
FF FE4Ch
FF FE48h
FF FE4Ah
FF FE46h
FF FE44h
UART Receive Data
Buffer
UART Transmit Data
Buffer
UART Baud Rate
Prescaler
UART Baud Rate
Divisor
UART Frame Select
Register
UART Mode Select
Register 1
UART Status Register
UART Interrupt Control
Register
UPSC
UDIV10:8
The Prescaler field specifies the prescaler val-
ue used for dividing the System Clock in the
first stage of the two-stage divider chain. For
the prescaler factors corresponding to each 5-
bit value, see Table 44.
The Baud Rate Divisor field holds the three
most significant bits (bits 10, 9, and 8) of the
UART baud rate divisor used in the second
stage of the two-stage divider chain. The re-
maining bits of the baud rate divisor are held
in the UBAUD register.
19.3.4 UART Baud Rate Divisor (UBAUD)
The UBAUD register is a byte-wide, read/write register that
contains the lower eight bits of the baud rate divisor. The
register contents are unknown at power-up and are left un-
changed by a reset operation. The register format is shown
below.
UOVR
UMDSL2
USPOS
FF FE50h
FF FE52h
FF FE54h
UART Oversample
Rate Register
UART Mode Select
Register 2
UART Sample
Position Register
7
UDIV7:0
0
UDIV7:0
The Baud Rate Divisor field holds the eight
lowest-order bits of the UART baud rate divi-
sor used in the second stage of the two-stage
divider chain. The three most significant bits
are held in the UPSR register. The divisor val-
ue used is (UDIV[10:0] + 1).
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