CP3BT10 Datasheet, PDF (119/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

19.3.5 UART Frame Select Register (UFRS)
19.3.6 UART Mode Select Register 1 (UMDSL1)
The UFRS register is a byte-wide, read/write register that
controls the frame format, including the number of data bits,
number of stop bits, and parity type. This register is cleared
upon reset. The register format is shown below.
7
6
54
3
2
10
The UMDSL1 register is a byte-wide, read/write register that
selects the clock source, synchronization mode, attention
mode, and line break generation. This register is cleared at
reset. When software writes to this register, the reserved
bits must be written with 0 for proper operation. The register
format is shown below.
Reserved UPEN UPSEL UXB9 USTP UCHAR
7
6
5
4
3
2
1
0
UCHAR
USTP
UXB9
UPSEL
UPEN
The Character Frame Format field selects the
number of data bits per frame, not including
the parity bit, as follows:
00 – 8 data bits per frame.
01 – 7 data bits per frame.
10 – 9 data bits per frame.
11 – Loop-back mode, 9 data bits per frame.
The Stop Bits bit specifies the number of stop
bits transmitted in each frame. If this bit is 0,
one stop bit is transmitted. If this bit is 1, two
stop bits are transmitted.
0 – One stop bit per frame.
1 – Two stop bits per frame.
The Transmit 9th Data Bit holds the value of
the ninth data bit, either 0 or 1, transmitted
when the UART is configured to transmit nine
data bits per frame. It has no effect when the
UART is configured to transmit seven or eight
data bits per frame.
The Parity Select field selects the treatment of
the parity bit. When the UART is configured to
transmit nine data bits per frame, the parity bit
is omitted and the UPSEL field is ignored.
00 – Odd parity.
01 – Even parity.
10 – No parity, transmit 1 (mark).
11 – No parity, transmit 0 (space).
The Parity Enable bit enables or disables par-
ity generation and parity checking. When the
UART is configured to transmit nine data bits
per frame, there is no parity bit and the UPEN
bit is ignored.
0 – Parity generation and checking disabled.
1 – Parity generation and checking enabled.
URTS UFCE UERD UETD Res. UBRK UATN Res.
UATN
UBRK
UETD
UERD
UFCE
URTS
The Attention Mode bit is used to enable At-
tention mode. When set, this bit selects the at-
tention mode of operation for the UART. When
clear, the attention mode is disabled. The
hardware clears this bit after an address
frame is received. An address frame is a 9-bit
character with a 1 in the ninth bit position.
0 – Attention mode disabled.
1 – Attention mode enabled.
The Force Transmission Break bit is used to
force the TXD output low. Setting this bit to 1
causes the TXD pin to go low. TXD remains
low until the UBRK bit is cleared by software.
0 – Normal operation.
1 – TXD pin forced low.
The Enable Transmit DMA bit controls wheth-
er DMA is used for UART transmit operations.
Enabling transmit DMA automatically disables
transmit interrupts, without regard to the state
of the UETI bit.
0 – Transmit DMA disabled.
1 – Transmit DMA enabled.
The Enable Receive DMA bit controls whether
DMA is used for UART receive operations.
Enabling receive DMA automatically disables
receive interrupts, without regard to the state
of the UERI bit. Receive error interrupts are
unaffected by the UERD bit.
0 – Receive DMA disabled.
1 – Receive DMA enabled.
The Flow Control Enable bit controls whether
flow control interrupts are enabled.
0 – Flow control interrupts disabled.
1 – Flow control interrupts enabled.
The Ready To Send bit directly controls the
state of the RTS output.
0 – RTS output is high.
1 – RTS output is low.
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