CP3BT10 Datasheet, PDF (3/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

2.0 CPU Features
CPU Features
„ Fully static RISC processor core, capable of operating
from 0 to 24 MHz with zero wait/hold states
„ Minimum 41.7 ns instruction cycle time with a 24-MHz in-
ternal clock frequency, based on a 12-MHz external input
„ 30 independently vectored peripheral interrupts
On-Chip Memory
„ 256K bytes reprogrammable Flash program memory
„ 8K bytes Flash data memory
„ 10K bytes of static RAM data memory
„ Addresses up to 8 Mbytes of external memory
Broad Range of Hardware Communications Peripherals
„ Bluetooth Lower Link Controller (LLC) including a shared
4.5K byte Bluetooth RAM and 1K byte Bluetooth Se-
quencer RAM
„ Full-speed USB node including seven Endpoint-FIFOs
conforming to USB 1.1 specification
„ ACCESS.bus serial bus (compatible with Philips I²C bus)
„ 8/16-bit SPI, Microwire/Plus serial interface
„ Universal Asynchronous Receiver/Transmitter (UART)
„ Advanced Audio Interface (AAI) to connect to external 8/
13-bit PCM Codecs as well as to ISDN-Controllers
through the IOM-2 interface (slave only)
„ CVSD/PCM converter supporting one bidirectional audio
connection
General-Purpose Hardware Peripherals
„ Dual 16-bit Multi-Function Timer
„ Versatile Timer Unit with four subsystems (VTU)
„ Four channel DMA controller
„ Timing and Watchdog Unit
Flexible I/O
„ Up to 37 general-purpose I/O pins (shared with on-chip
peripheral I/O pins)
„ Programmable I/O pin characteristics: TRI-STATE out-
put, push-pull output, weak pull-up input, high-imped-
ance input
„ Schmitt triggers on general purpose inputs
„ Multi-Input Wakeup
Extensive Power and Clock Management Support
„ On-chip Phase Locked Loop
„ Support for multiple clock options
„ Dual clock and reset
„ Power-down modes
Power Supply
„ I/O port operation at 2.5V to 3.3V
„ Core logic operation at 2.5V
„ On-chip power-on reset
Temperature Range
„ -40°C to +85°C (Industrial)
Packages
„ CSP-48, LQFP-100
Complete Development Environment
„ Pre-integrated hardware and software support for rapid
prototyping and production
„ Integrated environment
„ Project manager
„ Multi-file C source editor
„ High-level C source debugger
„ Comprehensive, integrated, one-stop technical support
Bluetooth Protocol Stack
„ Applications can interface to the high-level protocols or
directly to the low-level Host Controller Interface (HCI)
„ Transport layer support allows HCI command-based in-
terface over UART or USB port
„ Baseband (Link Controller) minimizes the performance
demand on the CPU
„ Link Manager (LM)
„ Logical Link Control and Adaptation Protocol (L2CAP)
„ Service Discovery Protocol (SDP)
„ RFCOMM Serial Port Emulation Protocol
„ All packet types, piconet, and scatternet functionality
supported
CP3BT10 Connectivity Processor Selection Guide
NSID
Speed
(MHz)
Temp. Range
Program
Flash
(kBytes)
Data
Flash
(kBytes)
SRAM
(kBytes)
External
Address
Lines
I/Os
Package
Type
Pack
Method
CP3BT10G38 24 -40° to +85°C 256
8
10
22
37 LQFP-100 Tray
CP3BT10G38X 24 -40° to +85°C 256
8
10
22
37 LQFP-100 1000-T&R
CP3BT10K38X 24 -40° to +85°C 256
8
10
0
21 CSP-48 2500-T&R
CP3BT10K38Y 24 -40° to +85°C 256
8
10
0
21 CSP-48 250-T&R
T&R = Tape and Reel
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