CP3BT10 Datasheet, PDF (146/210 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth and USB Interfaces

23.2.2 Mode 2: Input Capture
Mode 2 is the Input Capture mode, which measures the
elapsed time between occurrences of external events, and
which also provides a separate general-purpose timer/
counter.
Figure 64 is a block diagram of the Multi-Function Timer
configured to operate in Mode 2. The time base of the cap-
ture timer depends on Timer/Counter 1, which counts down
using the clock selected with the Timer/Counter 1 clock se-
lector. The TA pin functions as a capture input. A transition
received on the TA pin transfers the timer contents to the
TCRA register. The TA pin can be configured to sense either
rising or falling edges.
Timer 1
Clock
Capture A
TCRA
Preset
Timer/Counter 1
TCNT1
TAEN
Underflow
TAIEN
TAPND
TCPND
TCIEN
Timer
Interrupt 1
TA
Timer
Interrupt 1
Timer 2
Clock
Timer/Counter 2
TnCNT2
Underflow
TDPND
TDIEN
Timer
Interrupt 2
DS167
Figure 64. Input Capture Mode
The TA input can be configured to preset the counter to
FFFFh on reception of a valid capture event. In this case,
the current value of the counter is transferred to the corre-
sponding capture register and then the counter is preset to
FFFFh. Using this approach allows software to determine
the on-time and off-time and period of an external signal
with a minimum of CPU overhead.
In Mode 2, Timer/Counter 2 (TCNT2) can be used as a sim-
ple system timer. The clock counts down using the clock se-
lected with the Timer/Counter 2 clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TDIEN bit.
The values captured in the TCRA register at different times
reflect the elapsed time between transitions on the TA pin.
The input signal on the TA pin must have a pulse width equal
to or greater than one System Clock cycle.
There are two separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending bit. The
interrupt events are reception of a transition on the TA pin
and underflow of the TCNT1 counter. The enable bits for
these events are TAIEN and TCIEN, respectively.
www.national.com
146