MC908AP32CFBE Datasheet, PDF (99/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

SIM Bus Clock Control and Generation
Read: IF6
IF5
IF4
IF3
IF2
IF1
0
0
$FE04
Interrupt Status Register 1
(INT1)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
$FE05
Interrupt Status Register 2
(INT2)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: 0
$FE06
Interrupt Status Register 3
(INT3)
Write:
R
Reset: 0
IF21
IF20
IF19
IF18
IF17
IF16
IF15
R
R
R
R
R
R
R
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. SIM I/O Register Summary
7.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 6 Clock Generator Module
(CGM).)
OSC2
OSC1
OSCILLATOR (OSC) MODULE
OSCCLK
CGMXCLK
TO TBM
TO TIM, ADC
STOP MODE CLOCK
ENABLE SIGNALS
FROM CONFIG2
CGMRCLK
PHASE-LOCKED LOOP (PLL)
ICLK
CGMOUT
SIM COUNTER
SYSTEM INTEGRATION MODULE
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF MCU
IT23
TO REST
OF MCU
SIMDIV2
CGMVCLK
TO PWM
Figure 7-3. CGM Clock Signals
MONITOR MODE
USER MODE
PTB0
7.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the
divided PLL output (CGMPCLK) divided by four.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
99