MC908AP32CFBE Datasheet, PDF (98/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
INTERRUPT SOURCES
CPU INTERFACE
Addr.
Register Name
Bit 7
6
Read:
$FE00
SIM Break Status Register
(SBSR)
Write:
R
R
Reset: 0
0
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
$FE01
SIM Reset Status Register
(SRSR)
Write:
POR: 1
0
Read:
$FE03
SIM Break Flag Control
Register (SBFCR)
Write:
BCFE
R
Reset: 0
5
4
3
2
1
Bit 0
SBSW
R
R
R
R
R
NOTE
0
0
0
0
0
0
COP
ILOP
ILAD MODRST LVI
0
0
0
0
0
0
0
R
R
R
R
R
R
Figure 7-2. SIM I/O Register Summary
MC68HC908AP Family Data Sheet, Rev. 4
98
Freescale Semiconductor