MC908AP32CFBE Datasheet, PDF (211/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Chapter 13
Serial Peripheral Interface Module (SPI)
13.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex,
synchronous, serial communications with peripheral devices.
13.2 Features
Features of the SPI module include the following:
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four master mode frequencies (maximum = bus frequency ÷ 2)
• Maximum slave mode frequency = bus frequency
• Serial clock with programmable polarity and phase
• Two separately enabled interrupts:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
• Mode fault error flag with CPU interrupt capability
• Overflow error flag with CPU interrupt capability
• Programmable wired-OR mode
13.3 Pin Name Conventions and I/O Register Addresses
The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial
clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI
shares four I/O pins with four parallel I/O ports.
The full names of the SPI I/O pins are shown in Table 13-1. The generic pin names appear in the text that
follows.
Table 13-1. Pin Name Conventions
SPI Generic
Pin Names:
MISO
Full SPI
Pin Names:
SPI
PTC2/MISO
MOSI
PTC3/MOSI
SS
PTC4/SS
SPSCK
PTC5/SPSCK
CGND
V_SS
Figure 13-1 summarizes the SPI I/O registers.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
209