MC908AP32CFBE Datasheet, PDF(148/324 Page) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

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MC908AP32CFBE Datasheet, PDF (148/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

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Timer Interface Module (TIM)

NOTE

Before enabling a TIM channel register for input capture operation, make

sure that the TCHx pin is stable for at least two bus clocks.

TOVx â Toggle On Overï¬ow Bit

When channel x is an output compare channel, this read/write bit controls the behavior of the channel

x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no

effect.

Reset clears the TOVx bit.

1 = Channel x pin toggles on TIM counter overflow

0 = Channel x pin does not toggle on TIM counter overflow

NOTE

When TOVx is set, a TIM counter overflow takes precedence over a

channel x output compare if both occur at the same time.

CHxMAX â Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and

unbuffered PWM signals to 100%. As Figure 9-11 shows, the CHxMAX bit takes effect in the cycle

after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is

cleared.

OVERFLOW

OVERFLOW

PERIOD

TCHx

OVERFLOW

OVERFLOW OVERFLOW

CHxMAX

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

Figure 9-11. CHxMAX Latency

9.9.5 TIM Channel Registers

These read/write registers contain the captured TIM counter value of the input capture function or the

output compare value of the output compare function. The state of the TIM channel registers after reset

is unknown.

In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)

inhibits input captures until the low byte (TCHxL) is read.

In output compare mode (MSxB:MSxA â 0:0), writing to the high byte of the TIM channel x registers

(TCHxH) inhibits output compares until the low byte (TCHxL) is written.

MC68HC908AP Family Data Sheet, Rev. 4

148

Freescale Semiconductor

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