MC908AP32CFBE Datasheet, PDF (4/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Revision History
Date
January 2007
August 2005
October 2003
August 2003
July 2003
May 2003
Revision
Level
4
3
2.5
2.4
2.3
2.2
Description
15.7.2 ADC Clock Control Register — Changed “The ADC clock should
be set to between 500kHz and 2MHz” to “The ADC clock should be set
to between 500kHz and 1MHz”
Table 22-4 . DC Electrical Characteristics (5V) — Updated V_OL values.
Table 22-6 . Oscillator Specifications (5V) and Table 22-10 . Oscillator
Specifications (3V) — Corrected internal oscillator clock frequency,
f_ICLK. Updated crystal oscillator component values C_L, C₁, C₂, R_B, and
R_S.
Added MC68HC908AP16/AP8 information throughout.
Section 10. Monitor ROM (MON) — Corrected RAM address to $60.
Section 24. Electrical Specifications — Added run and wait I_DD data for
8MHz at 3V.
Section 24. Electrical Specifications — Updated stop I_DD data.
Removed MC68HC908AP16 references throughout.
Table 1-2 . Pin Functions — Added footnote for V_REG.
5.3 Configuration Register 1 (CONFIG1) — Clarified LVIPWRD and
LVIREGD bits.
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode — Updated
BSC bit behavior.
10.5 ROM-Resident Routines — Corrected data size limits and control
byte size for EE_READ and EE_WRITE.
Figure 12-2 . Timebase Control Register (TBCR) — Corrected register
address.
Section 24. Electrical Specifications — Updated.
Updated for f_NOM = 125kHz and filter components
in CGM section.
Updated electricals.
Page
Number(s)
254
299
301, 305
—
167
421
417, 421
—
30
67
125
168–193
207
415
101
415
MC68HC908AP Family Data Sheet, Rev. 4
4
Freescale Semiconductor