MC908AP32CFBE Datasheet, PDF (81/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Functional Description
Addr.
Register Name
Bit 7
6
5
4
$0036
Read:
PLL Control Register
(PTCL)
Write:
PLLIE
PLLF
PLLON
BCS
Reset: 0
0
1
0
$0037
PLL Bandwidth Control ^Read:
Register Write:
AUTO
LOCK
ACQ
0
(PBWC) Reset: 0
0
0
0
PLL Multiplier Select ^{Read: 0}
0
0
0
$0038
Register High Write:
(PMSH) Reset: 0
0
0
0
$0039
PLL Multiplier Select ^Read:
Register Low Write:
MUL7
MUL6
MUL5
MUL4
(PMSL) Reset: 0
1
0
0
$003A
PLL VCO Range Select ^Read:
Register Write:
VRS7
VRS6
VRS5
VRS4
(PMRS) Reset: 0
1
0
0
PLL Reference Divider ^{Read: 0}
0
0
0
$003B
Select Register Write:
(PMDS) Reset: 0
0
0
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
3
PRE1
0
0
2
PRE0
0
0
1
VPR1
0
0
0
MUL11
0
MUL3
0
VRS3
0
RDS3
0
R
0
MUL10
0
MUL2
0
VRS2
0
RDS2
0
= Reserved
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
Figure 6-2. CGM I/O Register Summary
Bit 0
VPR0
0
R
MUL8
0
MUL0
0
VRS0
0
RDS0
1
6.3.1 Oscillator Module
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module.
CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used
by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also
provides the reference clock for the timebase module (TBM). See Chapter 5 Oscillator (OSC) for detailed
oscillator circuit description. See Chapter 10 Timebase Module (TBM) for detailed description on TBM.
6.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
6.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency pre-scaler
• Modulo VCO frequency divider
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
81