MC908AP32CFBE Datasheet, PDF (244/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Multi-Master IIC Interface (MMIIC)
14.7.1 Data Sequence
(a) Master Transmit Mode
START
Address 0 ACK
TX Data1
ACK
TX DataN
ACK STOP
MMTXBE=0
MMRW=0
MMAST=1
Data1 → MMDTR
MMTXBE=1
MMTXIF=1
Data2 → MMDTR
MMTXBE=1
MMTXIF=1
Data3 → MMDTR
MMTXBE=1 MMNAKIF=1
MMTXIF=1 MMAST=0
DataN+2 → MMDTR MMTXBE=0
(b) Master Receive Mode
START
Address 1 ACK
RX Data1
ACK
RX DataN
NAK STOP
MMRXBF=0
MMRW=1
MMAST=1
MMTXBE=0
(dummy data → MMDTR)
Data1 → MMDRR
MMRXIF=1
MMRXBF=1
(c) Slave Transmit Mode
START
Address 1 ACK
TX Data1
ACK
DataN → MMDRR MMNAKIF=1
MMRXIF=1 ^MMAST=0
MMRXBF=1
TX DataN
NAK STOP
MMTXBE=1
MMRXBF=0
MMRXIF=1
MMRXBF=1
MMATCH=1
MMSRW=1
Data1 → MMDTR
MMTXBE=1
MMTXIF=1
Data2 → MMDTR
(d) Slave Receive Mode
START
Address 0 ACK
RX Data1
ACK
MMTXBE=1 MMNAKIF=1
MMTXIF=1 ^MMTXBE=0
DataN+2 → MMDTR
RX DataN
ACK STOP
MMTXBE=0
MMRXBF=0
MMRXIF=1
MMRXBF=1
MMATCH=1
MMSRW=0
Data1 → MMDRR
MMRXIF=1
MMRXBF=1
DataN → MMDRR
MMRXIF=1
MMRXBF=1
Shaded data packets indicate transmissions by the MCU
Figure 14-12. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
MC68HC908AP Family Data Sheet, Rev. 4
242
Freescale Semiconductor